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SystemVerilog project architecture examples

Interactive architecture diagrams of 57 open-source SystemVerilog repositories with a GitDiagram architecture diagram, most stars first. Each diagram shows the project's main components, how they connect, and links every part to its file on GitHub.

Repositories 1–50 of 57

  1. adam-maj/tiny-gpu★ 12.1k

    tiny-gpu is a minimal GPU hardware implementation written in SystemVerilog (src/*.sv) with Python/Cocotb tests (test/*.py).

  2. verilator/verilator★ 4k

    Verilator translates Verilog/SystemVerilog into optimized C++ or SystemC models, with optional lint, assertions, coverage, and JSON output; generated models can then be compiled…

  3. lowrisc/opentitan★ 3.6k

    OpenTitan is an open-source silicon Root of Trust spanning chip hardware, device firmware, cryptographic services, host tooling, manufacturing provisioning, and verification.

  4. lowrisc/ibex★ 2k

    - This is the Ibex RISC-V CPU core repository: a production-oriented, highly parameterized 32-bit SystemVerilog core.

  5. pulp-platform/axi★ 1.7k

    This repository is a synthesizable SystemVerilog component library for AXI4/ATOP and AXI4-Lite on-chip communication.

  6. hughperkins/verigpu★ 1.4k

  7. hdl-util/hdmi★ 1.3k

  8. fpganinja/taxi★ 880

  9. pulp-platform/common_cells★ 803

  10. dpretet/async_fifo★ 482

  11. roalogic/rv12★ 451

  12. baochip/baochip-1x★ 349

  13. chipsalliance/cores-veer-el2★ 326

  14. pulp-platform/croc★ 282

  15. openhwfoundation/cv32e40x★ 279

  16. intel/fpga-npu★ 265

  17. harishsg993010/tiny-npu★ 263

  18. chipsalliance/cores-veer-eh2★ 262

  19. eevaain/tiny-tpu★ 200

  20. kumarrishav14/axi★ 187

  21. xilinx/reconic★ 179

  22. godelmachine/ahb2★ 160

  23. chipsalliance/caliptra-rtl★ 159

  24. lowrisc/ariane★ 155

  25. accellera-official/uvm-core★ 150

  26. agalimberti/nocrouter★ 147

  27. bsc-loca/sauria★ 125

  28. siddhi-95/ahb-to-apb-bridge-verification★ 120

  29. ananthbhat94/ddr4memorycontroller★ 98

  30. abdelrhman-oun/ddr5_phy_writeoperation★ 85

  31. aignacio/axi_dma★ 81

  32. sach/system-verilog-packet-library★ 80

  33. akeelmedina22/risc-v-pipelined-processor★ 78

  34. pulp-platform/ita★ 68

  35. shehanmunasinghe/tinygpu★ 68

  36. dadongshangu/async_fifo★ 64

  37. anjali-287/spi-interface★ 55

  38. mbits-mirafra/axi4_avip★ 52

  39. zero-day-labs/riscv-aia★ 46

  40. adibis/brokenbench★ 36

  41. efinix-inc/evsoc★ 36

  42. georgeyhere/fpga-video-processing★ 35

  43. tenstorrent/tt-oca-harness-aou★ 35

  44. riverlane/qeciphy★ 34

  45. purdue-socet/atalla★ 29

  46. amd/mini-isp★ 26

  47. opencomputeproject/hwmgmt-module-dcscm-ltpi★ 26

  48. apriya-ram/axi_fifo_bfm★ 25

  49. intel/pfr-wilson-city★ 25

  50. donlon/axi-dma-controller★ 21

Counted over GitDiagram's stored diagrams of public repositories, from the names their components and groups carry and the files they link to; the rules are the ones in the 2026 open-source architecture report. Stars are GitHub's when the diagram was last made. Rebuilt daily: hubs grow as more repositories' languages are known.