How roalogic/rv12 works
RV12 is a configurable, single-issue RISC-V processor core. A system supplies instructions and data through its memory interface; the core fetches and executes instructions through its documented folded six-stage pipeline, then performs memory operations and writes results back to architectural state. Optional branch prediction, instruction/data caches, and debug are separate capabilities; memory protection and the AHB3-Lite adapter provide additional system-facing functionality. The README and tree support these product-level relationships, but no source excerpts were available to confirm detailed wiring or optional-feature dispatch.
Main entry points: riscv_core.sv RV12 core · riscv_mem.sv Memory stage · riscv_id.sv Instruction decode · riscv_if.sv Instruction fetch
Components 17
Execution pipeline
- RV12 core
rtl/verilog/core/riscv_core.sv - Instruction fetch
rtl/verilog/core/riscv_if.sv - Pre-decode
rtl/verilog/core/riscv_pd.sv - Instruction decode
rtl/verilog/core/riscv_id.sv - Execute
rtl/verilog/core/riscv_ex.sv - Memory stage
rtl/verilog/core/riscv_mem.sv - Writeback
rtl/verilog/core/riscv_wb.sv - Register file
rtl/verilog/core/riscv_rf.sv
Memory system
- Instruction cache
rtl/verilog/core/cache/riscv_icache_core.sv - Data cache
rtl/verilog/core/cache/riscv_dcache_core.sv - Memory protection
rtl/verilog/core/memory/riscv_pmpchk.sv
Optional features
- Branch prediction
rtl/verilog/core/riscv_bp.sv - Debug unit
rtl/verilog/core/riscv_du.sv - Core state
rtl/verilog/pkg/riscv_rv12_pkg.sv
System integration
- AHB3-Lite adapter
rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv
Other components
- SoC / software
- AHB3-Lite system
Connections 18
- SoC / software → RV12 core: supplies program
- RV12 core → Instruction fetch: fetches instructions
- Instruction fetch → Pre-decode: passes instructions
- Pre-decode → Instruction decode: passes decoded parcels
- Instruction decode → Execute: dispatches operations
- Execute → Memory stage: passes results
- Memory stage → Writeback: passes results
- Writeback → Register file: writes registers
- Register file → Instruction decode: provides operands
- RV12 core → Core state: uses configuration
- Instruction fetch → Instruction cache: may fetch through
- Memory stage → Data cache: may access through
- Memory stage → Memory protection: checks accesses
- Instruction decode → Branch prediction: may query
- RV12 core → Debug unit: may enable
- RV12 core → AHB3-Lite adapter: uses interface
- AHB3-Lite adapter → AHB3-Lite system: transfers requests
- AHB3-Lite system → AHB3-Lite adapter: returns responses