How intel/fpga-npu works
This repository implements an FPGA-oriented neural processing unit for low-latency inference, with software tooling to express workloads and a cycle-level C++ simulator. The main user path is a Keras model or workload being translated into NPU operations, then modeled by the simulator; the README also describes programming deployed FPGA hardware. The tree includes a PCIe kernel and user API as a separate access subsystem. Evidence is limited to the README, excerpts, and SOURCE INDEX references, so unsampled implementation links are omitted or marked unverified.
Main entry points: datapath.cpp NPU datapath · compiler.py NPU compiler · npu_layers.py NPU layers · npu_sim.cpp Simulator entry
Components 19
Workload software
- Keras model
- NPU layers
compiler/npu_layers.py - NPU compiler
compiler/compiler.py - Compiler driver
compiler/driver.py - Functional simulator
compiler/fsim.py - Example workloads
scripts/workloads
NPU simulator
- Simulator entry
simulator/main/npu_sim.cpp - Instruction loader
simulator/src/loader.cpp - Instruction decoder
simulator/src/decoder.cpp - NPU datapath
simulator/src/datapath.cpp - Matrix-vector unit
simulator/src/mvu.cpp - MVU tiles
simulator/src/tile.cpp - Processing elements
simulator/src/dpe.cpp - Element VRF
simulator/src/evrf.cpp - Vector functions
simulator/src/mfu.cpp - Pipeline channels
simulator/src/channel.cpp
PCIe access
- User PCIe API
patch/user/intel_fpga_pcie_api_linux.cpp - PCIe kernel driver
patch/kernel
Other components
- AI developer
Connections 21
- AI developer → Keras model: defines model
- AI developer → NPU compiler: programs workloads
- Keras model → NPU layers: compiles model
compiler/npu_layers.py - NPU layers → NPU compiler: builds operations
compiler/npu_layers.py - Compiler driver → NPU compiler: imports
compiler/driver.py - Compiler driver → NPU layers: imports
compiler/driver.py - NPU compiler → Functional simulator: uses model
compiler/compiler.py - Example workloads → NPU compiler: uses compiler
scripts/workloads/18_mlp3_1024_512_256_256.py - Example workloads → NPU layers: uses layers
scripts/workloads/18_mlp3_1024_512_256_256.py - Simulator entry → Instruction loader: loads instructions
- Simulator entry → Instruction decoder: runs decoder
- Simulator entry → NPU datapath: runs datapath
- NPU datapath → Matrix-vector unit: connects stage
- NPU datapath → Element VRF: connects stage
- NPU datapath → Vector functions: connects stages
- NPU datapath → Instruction loader: connects stage
- NPU datapath → Pipeline channels: transfers data
- Matrix-vector unit → MVU tiles: uses tiles
- MVU tiles → Processing elements: contains compute
- AI developer → User PCIe API: accesses device
- User PCIe API → PCIe kernel driver: device I/O