How tenstorrent/tt-oca-harness-aou works
AOU-RTL is an AXI4-to-UCIe FDI bridge IP. The principal workflow carries AXI transactions between chiplet-side AXI interfaces and the FDI data plane; integration can use a self-contained bringup wrapper or an externally managed FDI flow. APB provides configuration. The README documents parameterized FDI widths and the optional 3:1 AXI mux/splitter/aggregator. Internal links below are limited to the documented top-level roles and module naming; sampled source did not include RTL hierarchy or call wiring.
Main entry points: AOU_CORE.sv Protocol core · AOU_TOP.sv AOU_TOP · AOU_CORE_TOP.sv AOU_CORE_TOP · AOU_TX_CORE.sv TX core
Components 21
Integration
- AOU_TOP
RTL/AOU_TOP.sv - AOU_CORE_TOP
RTL/AOU_CORE_TOP.sv - FDI bringup
RTL/AOU_FDI_BRINGUP_CTRL.sv
Protocol Engine
- Protocol core
RTL/AOU_CORE.sv - TX core
RTL/AOU_TX_CORE.sv - RX core
RTL/AOU_RX_CORE.sv - TX FDI interface
RTL/AOU_TX_FDI_IF.sv - RX FDI interface
RTL/AOU_RX_FDI_IF.sv - TX AXI buffer
RTL/AOU_TX_AXI_BUFFER.sv
AXI Handling
- AXI mux splitter
RTL/AXI4MUX_3X1/AOU_AXI4MUX_3X1_TOP.v - Write aggregator
RTL/AXI4MUX_3X1/AOU_AGGREGATOR.v - AXI down path
RTL/AXI4MUX_3X1/AOU_AXI_DOWN.v - AXI up path
RTL/AXI4MUX_3X1/AOU_AXI_UP.v
Control and State
- Core registers
RTL/AOU_CORE_SFR.v - Activation control
RTL/AOU_ACTIVATION_CTRL.sv - Credit control
RTL/AOU_CRD_CTRL.sv - Early response table
RTL/AOU_EARLY_TABLE.sv - Error information
RTL/AOU_ERROR_INFO.sv
Other components
- AXI peers
- UCIe FDI
- APB host
Connections 19
- AXI peers → AOU_TOP: sends AXI
- AXI peers → AOU_CORE_TOP: sends AXI
- AOU_TOP → Protocol core: hosts engine
- AOU_CORE_TOP → Protocol core: hosts engine
- AOU_TOP → FDI bringup: includes bringup
- UCIe FDI → AOU_TOP: carries FDI
- UCIe FDI → AOU_CORE_TOP: carries FDI
- APB host → AOU_CORE_TOP: configures
- APB host → AOU_TOP: configures
- Protocol core → TX core: dispatches TX
- Protocol core → RX core: dispatches RX
- TX core → TX FDI interface: sends flits
- RX FDI interface → RX core: receives flits
- TX core → TX AXI buffer: buffers AXI
- APB host → Core registers: writes registers
- Protocol core → Activation control: controls activation
- Protocol core → Credit control: manages credits
- Protocol core → Early response table: tracks responses
- Protocol core → Error information: records errors