How pulp-platform/common_cells works
Common Cells is a reusable SystemVerilog RTL library, not an end-user application. A hardware designer selects and instantiates cells in a consuming design to implement clock/reset handling, crossings, datapaths, and other hardware functions. The README documents the library’s cell categories; no source excerpts were provided, so the graph shows documented capabilities and integration points without asserting internal call relationships.
Main entry points: cc_clk_int_div.sv Clock divider · cc_rstgen.sv Reset synchronizer · cc_cdc_2phase.sv Handshake CDC · cc_cdc_fifo_gray.sv CDC FIFO
Components 20
Clocks and CDC
- Clock divider
src/cc_clk_int_div.sv - Reset synchronizer
src/cc_rstgen.sv - Handshake CDC
src/cc_cdc_2phase.sv - CDC FIFO
src/cc_cdc_fifo_gray.sv - CDC reset control
src/cc_cdc_reset_ctrlr.sv - Pulse crossing
src/cc_edge_propagator.sv - Glitch-free mux
src/cc_clk_mux_glitch_free.sv
Counters and Logic
- Up/down counter
src/cc_counter.sv - LFSR
src/cc_lfsr.sv - ECC encoder
src/cc_ecc_encode.sv - ECC decoder
src/cc_ecc_decode.sv
Streams and Routing
- Stream FIFO
src/cc_stream_fifo.sv - Stream arbiter
src/cc_stream_arbiter.sv - Stream crossbar
src/cc_stream_xbar.sv - Stream adapters
src/cc_stream_upsizer.sv
Encoding and Addressing
- Address decode
src/cc_addr_decode.sv - Round-robin arbitration
src/cc_rr_arb_tree.sv - Memory banking
src/cc_mem_to_banks.sv - Bit utilities
src/cc_lzc.sv
Other components
- Hardware designer
Connections 19
- Hardware designer → Clock divider: instantiates
- Hardware designer → Reset synchronizer: instantiates
- Hardware designer → Handshake CDC: instantiates
- Hardware designer → CDC FIFO: instantiates
- Hardware designer → CDC reset control: instantiates
- Hardware designer → Pulse crossing: instantiates
- Hardware designer → Glitch-free mux: instantiates
- Hardware designer → Up/down counter: instantiates
- Hardware designer → LFSR: instantiates
- Hardware designer → ECC encoder: instantiates
- Hardware designer → ECC decoder: instantiates
- Hardware designer → Stream FIFO: instantiates
- Hardware designer → Stream arbiter: instantiates
- Hardware designer → Stream crossbar: instantiates
- Hardware designer → Stream adapters: instantiates
- Hardware designer → Address decode: instantiates
- Hardware designer → Round-robin arbitration: instantiates
- Hardware designer → Memory banking: instantiates
- Hardware designer → Bit utilities: instantiates