fpganinja/taxi

Purpose and entry points

Taxi is a SystemVerilog transport/IP library spanning on-chip buses, streaming data paths, Ethernet, PCIe, DMA, timing, and control. It also contains Corundum NIC implementations, Zircon IP-stack stages, host drivers, and board-targeted FPGA designs. Primary integration entry points are RTL top modules and file lists under src/*/rtl, plus board build targets such as src/cndm/board/Alveo/fpga/fpga_AU250/Makefile and src/eth/example/ZCU106/fpga/fpga_10g/Makefile.

Common transport fabric

APB, AXI, AXI-Lite, and AXI-Stream form the compositional boundary between components. Interface definitions establish typed bus contracts; adapters, interconnects/crossbars, FIFOs, registers, RAMs, and switches handle protocol conversion, routing, buffering, and clock-domain boundaries.

• src/axi/rtl/taxi_axi_if.sv

• src/axi/rtl/taxi_axi_crossbar.sv

• src/axis/rtl/taxi_axis_async_fifo.sv

DMA and PCIe host boundary

The DMA layer translates descriptors and segmented RAM accesses between client streams, AXI memory, and Xilinx UltraScale PCIe transports. The PCIe layer supplies host-controlled AXI-Lite access, MSI/MSI-X, configuration, VPD/VSEC, and interrupt-rate control. This is the principal FPGA-to-host boundary used by NIC designs.

• src/dma/rtl/taxi_dma_if_pcie_us.sv

• src/dma/rtl/taxi_axi_dma.sv

• src/pcie/rtl/taxi_pcie_us_axil_master.sv

Ethernet datapath and physical interfaces

Ethernet modules transform AXI-Stream frames through MAC, PCS/encoding, and PHY/transceiver-facing interfaces across MII/GMII/RGMII, 1000BASE-X, 10GBASE-R, 25GBASE-R, and USXGMII variants. MAC wrappers optionally include FIFOs and integrate control, pause handling, timestamps, and statistics; vendor-specific UltraScale GT wrappers form the hardware-facing edge.

• src/eth/rtl/taxi_eth_mac_10g.sv

• src/eth/rtl/taxi_eth_phy_10g.sv

• src/eth/rtl/us/taxi_eth_mac_25g_us.sv

Timing, statistics, and management plane

PTP distributes a central hardware clock into local clock domains; statistics collectors emit aggregated values over AXI-Stream and counters expose them through control registers. XFCP is a source-routed AXI-Stream control fabric, with UART ingress and bridges to APB, AXI, AXI-Lite, and I2C. Low-speed serial modules provide the physical/control endpoints.

• src/ptp/rtl/taxi_ptp_td_phc.sv

• src/stats/rtl/taxi_stats_collect.sv

• src/xfcp/rtl/taxi_xfcp_switch.sv

Corundum NIC and host software

cndm implements Corundum variants around PCIe, DMA queues, completion/event handling, and Ethernet ports. FPGA cores are wrapped per target board; the repository also ships a Linux kernel driver and a DPDK PMD, which define the host software boundary. cndm_proto is a separate simplified prototype path with its own RTL and driver.

• src/cndm/rtl/cndm_micro_core.sv

• src/cndm/modules/cndm/cndm_main.c

• src/cndm/dpdk/cndm/cndm_ethdev.c

Zircon and deployment/runtime environment

Zircon supplies pipelined IP RX parsing/egress and TX ingress/buffering/deparsing stages for application-facing packet processing. Board designs compose Taxi/CNDM or Ethernet blocks into Xilinx FPGA top levels, constraints, generated PCIe/DDR/GT IP, and Vivado builds. RTL is simulated with Cocotb/Python and Verilator; production synthesis depends on Xilinx Vivado and board-specific hardware.

• src/zircon/rtl/zircon_ip_rx_parse.sv

• src/zircon/rtl/zircon_ip_tx_deparse.sv

• src/cndm/board/Alveo/fpga/rtl/fpga_core.sv