How aignacio/axi_dma works
AXI DMA is an RTL IP that moves data between memory and programmed source/destination descriptors. A host configures descriptors and starts or aborts work through AXI4-Lite; the DMA FSM manages descriptor processing, streamers form AXI transfers, and the AXI master interface dispatches requests while a FIFO buffers transferred data. The README documents these principal relationships and capabilities, but the RTL excerpts were not provided, so finer wiring and the roles of wrapper modules are not inferred.
Main entry points: dma_streamer.sv Streamers · dma_axi_wrapper.sv AXI4-Lite slave · dma_axi_if.sv AXI master interface · dma_fsm.sv DMA FSM
Components 10
Control and data path
- DMA FSM
rtl/dma_fsm.sv - Streamers
rtl/dma_streamer.sv - Data FIFO
rtl/dma_fifo.sv - Function wrapper
rtl/dma_func_wrapper.sv
Bus interfaces
- AXI wrapper
rtl/dma_axi_wrapper.sv - AXI master interface
rtl/dma_axi_if.sv - AXI4-Lite slave
rtl/dma_axi_wrapper.sv
Registers
- CSR block
csr_out/csr_dma.sv
Other components
- Host
- AXI memory
Connections 7
- Host → AXI4-Lite slave: programs CSRs
README.md - AXI4-Lite slave → CSR block: accesses registers
- DMA FSM → Streamers: dispatches descriptors
README.md - Streamers → AXI master interface: requests transfers
README.md - AXI master interface → AXI memory: reads and writes
README.md - Streamers → Data FIFO: buffers data
README.md - AXI wrapper → AXI4-Lite slave: exposes interface