How ananthbhat94/ddr4memorycontroller works
DDR4MemoryController accepts cache read/write requests carrying a 32-bit address and 64 bytes of write data, queues up to eight requests, and supports open-page policy and out-of-order execution. The documented simulation top integrates a CacheBFM and a Memory BFM. Filenames identify likely controller and DDR4-interface responsibilities, but no source excerpts were available to confirm how those modules call or connect, so the graph limits internal wiring to documented relationships.
Main entry points: MemoryController.sv Memory controller · Top.sv Cache BFM
Components 17
Simulation endpoints
- Cache BFM
Top.sv - Simulation top
Top.sv - Memory BFM
Top.sv
Memory control
- Memory controller
MemoryController.sv - Request queue
MemoryController.sv - Out-of-order scheduler
Scheduler.sv - Controller FSM
Controller_FSM.sv - Receive command
Receive_command.sv - Send command
Send_command.sv - Read data communication
Read_data_comm.sv
DDR4 operations
- DDR4 interface
DDR4Interface.sv - Read/write handling
ReadWrite.sv - Memory model
Memory.sv - Cache-to-memory interface
C2MInterface.sv - Timing calculation
CalcMax.sv - Shift register
ShiftReg.sv - Timer
Timer.sv
Connections 2
- Cache BFM → Memory controller: sends requests
- Memory controller → Request queue: queues requests