How userofmeet/sky130_standard_cell_library works
This repository is a SKY130A standard-cell library project. Its main workflow develops buffer, NAND, and D flip-flop cells, implements and verifies their layouts, extracts parasitics, and characterizes timing, power, and input capacitance to produce library deliverables. The README documents the flow and tools, but no source excerpts were provided, so links reflect only documented stages; detailed tool invocation and artifact dependencies are not inferred.
Main entry points: layout Magic layouts · spice_netlist Schematic netlists · testbenches Cell characterization · charlib CharLib configuration
Components 15
Cell design
- Schematic netlists
spice_netlist - Verilog models
verilog
Physical implementation
- Magic layouts
layout - PEX netlists
spice_netlist
Characterization
- SPICE testbenches
testbenches - Cell characterization
testbenches
Library deliverables
- CharLib configuration
charlib - Liberty files
charlib - LEF files
lef - Project report
Team10_EE671_Course_Project1_Report.pdf
Other components
- Cell designer
- SKY130A PDK
- Magic VLSI
- Netgen LVS
- NGSpice
Connections 17
- Cell designer → Schematic netlists: designs cells
- SKY130A PDK → Schematic netlists: provides process
- Cell designer → Verilog models: develops models
- Cell designer → Magic layouts: designs layouts
- SKY130A PDK → Magic layouts: provides process
- Magic layouts → Magic VLSI: DRC checks
- Schematic netlists → Netgen LVS: LVS reference
- Magic layouts → Netgen LVS: LVS comparison
- Magic layouts → PEX netlists: extracts parasitics
- Schematic netlists → NGSpice: pre-layout simulation
- SPICE testbenches → NGSpice: drives simulations
- PEX netlists → NGSpice: post-layout simulation
- NGSpice → Cell characterization: produces measurements
- Cell characterization → CharLib configuration: characterizes cells
- CharLib configuration → Liberty files: generates tables
- Magic layouts → LEF files: exports geometry
- Cell designer → Project report: documents results