How evensgn/risc-v-cpu works
The product is a five-stage RV32I-subset CPU implemented in Verilog, with forwarding, caches, and a UART link for accessing a PC-hosted memory simulator. The main hardware workflow is instruction fetch through execute, memory access, and writeback; the alternate host workflow loads a program and runs either the instruction simulator or UART protocol handler against an environment-managed memory. Pipeline and UART capabilities are documented in the README; detailed hardware wiring was not sampled, so the graph omits uncertain module-level connections.
Main entry points: environment.cpp Memory environment · riscv_cpu.v RISC-V CPU · stage_id.v Decode · stage_ex.v Execute
Components 18
CPU pipeline
- RISC-V CPU
src/cpu/riscv_cpu.v - Instruction fetch
src/cpu/stage_if.v - Decode
src/cpu/stage_id.v - Execute
src/cpu/stage_ex.v - Memory stage
src/cpu/stage_mem.v - Pipeline registers
src/cpu/reg_if_id.v - Control and forwarding
src/cpu/ctrl.v - Register file
src/cpu/regfile.v - Instruction/data caches
src/cpu/cache.v - Memory controller
src/cpu/mem_ctrl.v
UART interface
- UART transport
src/cpu/uart_trans.v
Host memory simulator
- Simulator entry
src/memory/main.cpp - Memory environment
src/memory/environment.cpp - Instruction simulator
src/memory/simulator.cpp - UART adapter
src/memory/adapter.cpp
Other components
- Program input
- FPGA / PC
- Serial port
Connections 21
- Program input → Simulator entry: provides program
- Simulator entry → Memory environment: starts run
- Memory environment → Instruction simulator: runs instructions
- Instruction simulator → Memory environment: reads/writes memory
- Memory environment → UART adapter: dispatches received bytes
- UART adapter → Memory environment: reads/writes memory
- UART adapter → Memory environment: sends UART data
- Memory environment → Serial port: reads/writes bytes
- FPGA / PC → Serial port: UART link
- RISC-V CPU → Instruction fetch: runs pipeline
- Instruction fetch → Decode: passes instructions
- Decode → Execute: passes operands
- Execute → Memory stage: passes results
- Memory stage → RISC-V CPU: returns results
- Decode → Register file: reads registers
- Execute → Register file: writes results
- Control and forwarding → RISC-V CPU: controls stalls and forwarding
- RISC-V CPU → Instruction/data caches: uses instruction/data caches
- RISC-V CPU → Memory controller: accesses memory
- Memory controller → UART transport: transfers memory requests
- UART transport → FPGA / PC: communicates with PC