How pulp-platform/cheshire works
Cheshire is a configurable, minimal Linux-capable RISC-V host platform built around CVA6, intended to boot autonomously and serve as a host for accelerator systems. The principal software path is boot ROM selection of a boot source, loading a zero-stage loader, then loading and launching firmware (and a device tree for GPT disk boot). Hardware sources define the SoC and register map; software includes device interfaces and flash utilities. The README documents simulation and target support, but most hardware composition and target wiring were not shown in the sampled source.
Main entry points: cheshire_bootrom.c Boot ROM · zsl.c Zero-stage loader · flash.c Disk flasher · cheshire_soc.sv Cheshire SoC
Components 18
SoC Platform
- Cheshire SoC
hw/cheshire_soc.sv - SoC address map
hw/cheshire.rdl - Generated SoC registers
hw/regs/cheshire_soc_regs.sv
Boot and Storage
- Boot ROM
hw/bootrom/cheshire_bootrom.c - GPT boot logic
sw/lib/gpt.c - Zero-stage loader
sw/boot/zsl.c - Disk flasher
sw/boot/flash.c
Software Interfaces
- SD card HAL
sw/lib/hal/spi_sdcard.c - SPI flash HAL
sw/lib/hal/spi_s25fs512s.c - I2C EEPROM HAL
sw/lib/hal/i2c_24fc1025.c - UART interface
sw/lib/dif/uart.c - Timer interface
sw/lib/dif/clint.c - Register definitions
sw/include/regs/cheshire.h
Execution Targets
- Simulation target
target/sim/src/tb_cheshire_soc.sv - Xilinx FPGA target
target/xilinx/src/cheshire_top_xilinx.sv
Other components
- System host
- Firmware payload
- Boot media
Connections 19
- System host → Cheshire SoC: hosts
README.md - Boot ROM → GPT boot logic: boots via GPT
hw/bootrom/cheshire_bootrom.c - Boot ROM → SD card HAL: reads SD
hw/bootrom/cheshire_bootrom.c - Boot ROM → SPI flash HAL: reads flash
hw/bootrom/cheshire_bootrom.c - Boot ROM → I2C EEPROM HAL: reads EEPROM
hw/bootrom/cheshire_bootrom.c - Boot ROM → UART interface: serves debug
hw/bootrom/cheshire_bootrom.c - Boot ROM → Timer interface: measures clock
hw/bootrom/cheshire_bootrom.c - Boot ROM → Register definitions: reads boot config
hw/bootrom/cheshire_bootrom.c - GPT boot logic → Boot media: reads partitions
- Zero-stage loader → GPT boot logic: finds partitions
sw/boot/zsl.c - Zero-stage loader → UART interface: initializes console
sw/boot/zsl.c - Zero-stage loader → Timer interface: measures clock
sw/boot/zsl.c - Zero-stage loader → Register definitions: reads boot config
sw/boot/zsl.c - Zero-stage loader → Firmware payload: loads and launches
sw/boot/zsl.c - Disk flasher → SD card HAL: writes blocks
sw/boot/flash.c - Disk flasher → SPI flash HAL: flashes sectors
sw/boot/flash.c - Disk flasher → I2C EEPROM HAL: writes EEPROM
sw/boot/flash.c - Cheshire SoC → Simulation target: simulated by
README.md - Cheshire SoC → Xilinx FPGA target: target implementation