# userofmeet/sky130_standard_cell_library architecture

> Architecture diagram of the GitHub repository userofmeet/sky130_standard_cell_library, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-26). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/userofmeet/sky130_standard_cell_library
- Repository: https://github.com/userofmeet/sky130_standard_cell_library

## Overview

This repository is a SKY130A standard-cell library project. Its main workflow develops buffer, NAND, and D flip-flop cells, implements and verifies their layouts, extracts parasitics, and characterizes timing, power, and input capacitance to produce library deliverables. The README documents the flow and tools, but no source excerpts were provided, so links reflect only documented stages; detailed tool invocation and artifact dependencies are not inferred.

Main entry points: [`layout`](https://github.com/userofmeet/sky130_standard_cell_library/tree/main/layout) (Magic layouts), [`spice_netlist`](https://github.com/userofmeet/sky130_standard_cell_library/tree/main/spice_netlist) (Schematic netlists), [`testbenches`](https://github.com/userofmeet/sky130_standard_cell_library/tree/main/testbenches) (Cell characterization), [`charlib`](https://github.com/userofmeet/sky130_standard_cell_library/tree/main/charlib) (CharLib configuration)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_design["Cell design"]
  node_schematics["Schematic netlists"]
  node_verilog["Verilog models"]
end

subgraph group_physical["Physical implementation"]
  node_layouts["Magic layouts"]
  node_pex["PEX netlists"]
end

subgraph group_characterization["Characterization"]
  node_testbenches["SPICE testbenches"]
  node_metrics["Cell characterization"]
end

subgraph group_deliverables["Library deliverables"]
  node_charlib["CharLib configuration"]
  node_liberty["Liberty files"]
  node_lef["LEF files"]
  node_report["Project report"]
end

node_engineer(("Cell designer"))
node_pdk["SKY130A PDK"]
node_magic["Magic VLSI"]
node_netgen["Netgen LVS"]
node_ngspice["NGSpice"]

node_engineer -->|"designs cells"| node_schematics
node_pdk -->|"provides process"| node_schematics
node_engineer -->|"develops models"| node_verilog
node_engineer -->|"designs layouts"| node_layouts
node_pdk -->|"provides process"| node_layouts
node_layouts -->|"DRC checks"| node_magic
node_schematics -->|"LVS reference"| node_netgen
node_layouts -->|"LVS comparison"| node_netgen
node_layouts -->|"extracts parasitics"| node_pex
node_schematics -->|"pre-layout simulation"| node_ngspice
node_testbenches -->|"drives simulations"| node_ngspice
node_pex -->|"post-layout simulation"| node_ngspice
node_ngspice -->|"produces measurements"| node_metrics
node_metrics -->|"characterizes cells"| node_charlib
node_charlib -->|"generates tables"| node_liberty
node_layouts -->|"exports geometry"| node_lef
node_engineer -->|"documents results"| node_report

click node_schematics "https://github.com/userofmeet/sky130_standard_cell_library/tree/main/spice_netlist"
click node_verilog "https://github.com/userofmeet/sky130_standard_cell_library/tree/main/verilog"
click node_layouts "https://github.com/userofmeet/sky130_standard_cell_library/tree/main/layout"
click node_pex "https://github.com/userofmeet/sky130_standard_cell_library/tree/main/spice_netlist"
click node_testbenches "https://github.com/userofmeet/sky130_standard_cell_library/tree/main/testbenches"
click node_metrics "https://github.com/userofmeet/sky130_standard_cell_library/tree/main/testbenches"
click node_charlib "https://github.com/userofmeet/sky130_standard_cell_library/tree/main/charlib"
click node_liberty "https://github.com/userofmeet/sky130_standard_cell_library/tree/main/charlib"
click node_lef "https://github.com/userofmeet/sky130_standard_cell_library/tree/main/lef"
click node_report "https://github.com/userofmeet/sky130_standard_cell_library/blob/main/Team10_EE671_Course_Project1_Report.pdf"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_schematics,node_verilog toneBlue
class node_layouts,node_pex toneAmber
class node_testbenches,node_metrics toneMint
class node_charlib,node_liberty,node_lef,node_report toneRose
class node_engineer,node_pdk,node_magic,node_netgen,node_ngspice toneIndigo
```

## Components

### Cell design

- [Schematic netlists](https://github.com/userofmeet/sky130_standard_cell_library/tree/main/spice_netlist): `spice_netlist`
- [Verilog models](https://github.com/userofmeet/sky130_standard_cell_library/tree/main/verilog): `verilog`

### Physical implementation

- [Magic layouts](https://github.com/userofmeet/sky130_standard_cell_library/tree/main/layout): `layout`
- [PEX netlists](https://github.com/userofmeet/sky130_standard_cell_library/tree/main/spice_netlist): `spice_netlist`

### Characterization

- [SPICE testbenches](https://github.com/userofmeet/sky130_standard_cell_library/tree/main/testbenches): `testbenches`
- [Cell characterization](https://github.com/userofmeet/sky130_standard_cell_library/tree/main/testbenches): `testbenches`

### Library deliverables

- [CharLib configuration](https://github.com/userofmeet/sky130_standard_cell_library/tree/main/charlib): `charlib`
- [Liberty files](https://github.com/userofmeet/sky130_standard_cell_library/tree/main/charlib): `charlib`
- [LEF files](https://github.com/userofmeet/sky130_standard_cell_library/tree/main/lef): `lef`
- [Project report](https://github.com/userofmeet/sky130_standard_cell_library/blob/main/Team10_EE671_Course_Project1_Report.pdf): `Team10_EE671_Course_Project1_Report.pdf`

### Other components

- **Cell designer**
- **SKY130A PDK**
- **Magic VLSI**
- **Netgen LVS**
- **NGSpice**

## Connections

- Cell designer → Schematic netlists: designs cells
- SKY130A PDK → Schematic netlists: provides process
- Cell designer → Verilog models: develops models
- Cell designer → Magic layouts: designs layouts
- SKY130A PDK → Magic layouts: provides process
- Magic layouts → Magic VLSI: DRC checks
- Schematic netlists → Netgen LVS: LVS reference
- Magic layouts → Netgen LVS: LVS comparison
- Magic layouts → PEX netlists: extracts parasitics
- Schematic netlists → NGSpice: pre-layout simulation
- SPICE testbenches → NGSpice: drives simulations
- PEX netlists → NGSpice: post-layout simulation
- NGSpice → Cell characterization: produces measurements
- Cell characterization → CharLib configuration: characterizes cells
- CharLib configuration → Liberty files: generates tables
- Magic layouts → LEF files: exports geometry
- Cell designer → Project report: documents results