# roalogic/rv12 architecture

> Architecture diagram of the GitHub repository roalogic/rv12, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-25). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/roalogic/rv12
- Repository: https://github.com/roalogic/rv12

## Overview

RV12 is a configurable, single-issue RISC-V processor core. A system supplies instructions and data through its memory interface; the core fetches and executes instructions through its documented folded six-stage pipeline, then performs memory operations and writes results back to architectural state. Optional branch prediction, instruction/data caches, and debug are separate capabilities; memory protection and the AHB3-Lite adapter provide additional system-facing functionality. The README and tree support these product-level relationships, but no source excerpts were available to confirm detailed wiring or optional-feature dispatch.

Main entry points: [`rtl/verilog/core/riscv_core.sv`](https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_core.sv) (RV12 core), [`rtl/verilog/core/riscv_mem.sv`](https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_mem.sv) (Memory stage), [`rtl/verilog/core/riscv_id.sv`](https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_id.sv) (Instruction decode), [`rtl/verilog/core/riscv_if.sv`](https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_if.sv) (Instruction fetch)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_pipeline["Execution pipeline"]
  node_core["RV12 core<br/>[riscv_core.sv]"]
  node_if["Instruction fetch<br/>[riscv_if.sv]"]
  node_pd["Pre-decode<br/>[riscv_pd.sv]"]
  node_id["Instruction decode<br/>[riscv_id.sv]"]
  node_ex["Execute<br/>[riscv_ex.sv]"]
  node_mem["Memory stage<br/>[riscv_mem.sv]"]
  node_wb["Writeback<br/>[riscv_wb.sv]"]
  node_rf["Register file<br/>[riscv_rf.sv]"]
end

subgraph group_memory["Memory system"]
  node_icache["Instruction cache"]
  node_dcache["Data cache"]
  node_protection["Memory protection<br/>[riscv_pmpchk.sv]"]
end

subgraph group_features["Optional features"]
  node_bpu["Branch prediction<br/>[riscv_bp.sv]"]
  node_debug["Debug unit<br/>[riscv_du.sv]"]
  node_state["Core state<br/>[riscv_rv12_pkg.sv]"]
end

subgraph group_system["System integration"]
  node_ahb["AHB3-Lite adapter"]
end

node_soc(("SoC / software"))
node_bus(("AHB3-Lite system"))

node_soc -->|"supplies program"| node_core
node_core -->|"fetches instructions"| node_if
node_if -->|"passes instructions"| node_pd
node_pd -->|"passes decoded parcels"| node_id
node_id -->|"dispatches operations"| node_ex
node_ex -->|"passes results"| node_mem
node_mem -->|"passes results"| node_wb
node_wb -->|"writes registers"| node_rf
node_rf -->|"provides operands"| node_id
node_core -->|"uses configuration"| node_state
node_if -.->|"may fetch through"| node_icache
node_mem -.->|"may access through"| node_dcache
node_mem -->|"checks accesses"| node_protection
node_id -.->|"may query"| node_bpu
node_core -.->|"may enable"| node_debug
node_core -->|"uses interface"| node_ahb
node_ahb -->|"transfers requests"| node_bus
node_bus -->|"returns responses"| node_ahb

click node_core "https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_core.sv"
click node_if "https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_if.sv"
click node_pd "https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_pd.sv"
click node_id "https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_id.sv"
click node_ex "https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_ex.sv"
click node_mem "https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_mem.sv"
click node_wb "https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_wb.sv"
click node_rf "https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_rf.sv"
click node_icache "https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/cache/riscv_icache_core.sv"
click node_dcache "https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/cache/riscv_dcache_core.sv"
click node_protection "https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/memory/riscv_pmpchk.sv"
click node_bpu "https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_bp.sv"
click node_debug "https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_du.sv"
click node_state "https://github.com/roalogic/rv12/blob/master/rtl/verilog/pkg/riscv_rv12_pkg.sv"
click node_ahb "https://github.com/roalogic/rv12/blob/master/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_core,node_if,node_pd,node_id,node_ex,node_mem,node_wb,node_rf toneBlue
class node_icache,node_dcache,node_protection toneAmber
class node_bpu,node_debug,node_state toneMint
class node_ahb toneRose
class node_soc,node_bus toneIndigo
```

## Components

### Execution pipeline

- [RV12 core](https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_core.sv): `rtl/verilog/core/riscv_core.sv`
- [Instruction fetch](https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_if.sv): `rtl/verilog/core/riscv_if.sv`
- [Pre-decode](https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_pd.sv): `rtl/verilog/core/riscv_pd.sv`
- [Instruction decode](https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_id.sv): `rtl/verilog/core/riscv_id.sv`
- [Execute](https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_ex.sv): `rtl/verilog/core/riscv_ex.sv`
- [Memory stage](https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_mem.sv): `rtl/verilog/core/riscv_mem.sv`
- [Writeback](https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_wb.sv): `rtl/verilog/core/riscv_wb.sv`
- [Register file](https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_rf.sv): `rtl/verilog/core/riscv_rf.sv`

### Memory system

- [Instruction cache](https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/cache/riscv_icache_core.sv): `rtl/verilog/core/cache/riscv_icache_core.sv`
- [Data cache](https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/cache/riscv_dcache_core.sv): `rtl/verilog/core/cache/riscv_dcache_core.sv`
- [Memory protection](https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/memory/riscv_pmpchk.sv): `rtl/verilog/core/memory/riscv_pmpchk.sv`

### Optional features

- [Branch prediction](https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_bp.sv): `rtl/verilog/core/riscv_bp.sv`
- [Debug unit](https://github.com/roalogic/rv12/blob/master/rtl/verilog/core/riscv_du.sv): `rtl/verilog/core/riscv_du.sv`
- [Core state](https://github.com/roalogic/rv12/blob/master/rtl/verilog/pkg/riscv_rv12_pkg.sv): `rtl/verilog/pkg/riscv_rv12_pkg.sv`

### System integration

- [AHB3-Lite adapter](https://github.com/roalogic/rv12/blob/master/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv): `rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv`

### Other components

- **SoC / software**
- **AHB3-Lite system**

## Connections

- SoC / software → RV12 core: supplies program
- RV12 core → Instruction fetch: fetches instructions
- Instruction fetch → Pre-decode: passes instructions
- Pre-decode → Instruction decode: passes decoded parcels
- Instruction decode → Execute: dispatches operations
- Execute → Memory stage: passes results
- Memory stage → Writeback: passes results
- Writeback → Register file: writes registers
- Register file → Instruction decode: provides operands
- RV12 core → Core state: uses configuration
- Instruction fetch → Instruction cache: may fetch through
- Memory stage → Data cache: may access through
- Memory stage → Memory protection: checks accesses
- Instruction decode → Branch prediction: may query
- RV12 core → Debug unit: may enable
- RV12 core → AHB3-Lite adapter: uses interface
- AHB3-Lite adapter → AHB3-Lite system: transfers requests
- AHB3-Lite system → AHB3-Lite adapter: returns responses