How sneha-prathipati/rv32i-pipelined-risc-v-processor works
This is a modular 32-bit RV32I processor. Its principal workflow is instruction fetch, decode, execute, memory access, and write-back, with pipeline registers between stages; forwarding and hazard handling support that flow. The README also documents instruction and data caches, branch prediction, and performance monitoring. Relationships below follow those documented capabilities. Source excerpts were unavailable, so detailed wiring—especially cache refill, control, and monitoring connections—is not inferred.
Main entry points: ex_stage.v Execute stage · if_stage.v Instruction fetch · id_stage.v Instruction decode · mem_stage.v Memory stage
Components 23
Pipeline
- Processor top
rv32i_pipeline_top.v - Instruction fetch
if_stage.v - IF/ID register
if_id.v - ID/EX register
id_ex.v - EX/MEM register
ex_mem.v - MEM/WB register
mem_wb.v - Write-back stage
wb_stage.v
Decode and Execute
- Instruction decode
id_stage.v - Execute stage
ex_stage.v - ALU and control
alu.v - Register file
register_file.v - Hazard detection
hazard_detection.v - Data forwarding
forwarding_unit.v
Memory System
- Memory stage
mem_stage.v - Instruction cache
instruction_cache.v - Data cache
data_cache.v - Cache controller
cache_controller.v - Cache refill
cache_refill.v
Branch Control
- Branch predictor
branch_predictor.v - Branch statistics
branch_stats.v
Performance Monitoring
- CPI monitor
cpi_monitor.v - Cache monitor
cache_monitor.v
Other components
- Instruction workload
Connections 18
- Instruction workload → Processor top: provides instructions
- Processor top → Instruction fetch: starts pipeline
- Instruction fetch → IF/ID register: passes fetched instruction
- IF/ID register → Instruction decode: passes instruction
- Instruction decode → ID/EX register: passes decoded values
- ID/EX register → Execute stage: passes operands
- Execute stage → EX/MEM register: passes results
- EX/MEM register → Memory stage: passes memory operation
- Memory stage → MEM/WB register: passes result
- MEM/WB register → Write-back stage: passes result
- Instruction fetch → Instruction cache: fetches instructions
- Memory stage → Data cache: accesses data
- Instruction decode → Register file: reads registers
- Write-back stage → Register file: writes registers
- Execute stage → ALU and control: computes operations
- Hazard detection → Processor top: controls stalls and flushes
- Data forwarding → Execute stage: forwards operands
- Branch predictor → Branch statistics: records predictions