# sneha-prathipati/rv32i-pipelined-risc-v-processor architecture

> Architecture diagram of the GitHub repository sneha-prathipati/rv32i-pipelined-risc-v-processor, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-28). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/sneha-prathipati/rv32i-pipelined-risc-v-processor
- Repository: https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor

## Overview

This is a modular 32-bit RV32I processor. Its principal workflow is instruction fetch, decode, execute, memory access, and write-back, with pipeline registers between stages; forwarding and hazard handling support that flow. The README also documents instruction and data caches, branch prediction, and performance monitoring. Relationships below follow those documented capabilities. Source excerpts were unavailable, so detailed wiring—especially cache refill, control, and monitoring connections—is not inferred.

Main entry points: [`ex_stage.v`](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/ex_stage.v) (Execute stage), [`if_stage.v`](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/if_stage.v) (Instruction fetch), [`id_stage.v`](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/id_stage.v) (Instruction decode), [`mem_stage.v`](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/mem_stage.v) (Memory stage)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_pipeline["Pipeline"]
  node_processor["Processor top"]
  node_fetch["Instruction fetch<br/>[if_stage.v]"]
  node_ifid["IF/ID register<br/>[if_id.v]"]
  node_idex["ID/EX register<br/>[id_ex.v]"]
  node_exmem["EX/MEM register<br/>[ex_mem.v]"]
  node_memwb["MEM/WB register<br/>[mem_wb.v]"]
  node_writeback["Write-back stage<br/>[wb_stage.v]"]
end

subgraph group_execution["Decode and Execute"]
  node_decode["Instruction decode<br/>[id_stage.v]"]
  node_execute["Execute stage<br/>[ex_stage.v]"]
  node_alu["ALU and control<br/>[alu.v]"]
  node_register_file["Register file<br/>[register_file.v]"]
  node_hazards["Hazard detection<br/>[hazard_detection.v]"]
  node_forwarding["Data forwarding<br/>[forwarding_unit.v]"]
end

subgraph group_memory["Memory System"]
  node_memory_stage["Memory stage<br/>[mem_stage.v]"]
  node_instruction_cache[("Instruction cache")]
  node_data_cache[("Data cache<br/>[data_cache.v]")]
  node_cache_control["Cache controller<br/>[cache_controller.v]"]
  node_cache_refill["Cache refill<br/>[cache_refill.v]"]
end

subgraph group_branch["Branch Control"]
  node_branch_predictor["Branch predictor<br/>[branch_predictor.v]"]
  node_branch_stats["Branch statistics<br/>[branch_stats.v]"]
end

subgraph group_monitoring["Performance Monitoring"]
  node_cpi_monitor["CPI monitor<br/>[cpi_monitor.v]"]
  node_cache_monitor["Cache monitor<br/>[cache_monitor.v]"]
end

node_workload(("Instruction workload"))

node_workload -->|"provides instructions"| node_processor
node_processor -->|"starts pipeline"| node_fetch
node_fetch -->|"passes fetched instruction"| node_ifid
node_ifid -->|"passes instruction"| node_decode
node_decode -->|"passes decoded values"| node_idex
node_idex -->|"passes operands"| node_execute
node_execute -->|"passes results"| node_exmem
node_exmem -->|"passes memory operation"| node_memory_stage
node_memory_stage -->|"passes result"| node_memwb
node_memwb -->|"passes result"| node_writeback
node_fetch -->|"fetches instructions"| node_instruction_cache
node_memory_stage -->|"accesses data"| node_data_cache
node_decode -->|"reads registers"| node_register_file
node_writeback -->|"writes registers"| node_register_file
node_execute -->|"computes operations"| node_alu
node_hazards -->|"controls stalls and flushes"| node_processor
node_forwarding -->|"forwards operands"| node_execute
node_branch_predictor -->|"records predictions"| node_branch_stats

click node_processor "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/rv32i_pipeline_top.v"
click node_fetch "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/if_stage.v"
click node_ifid "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/if_id.v"
click node_decode "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/id_stage.v"
click node_idex "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/id_ex.v"
click node_execute "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/ex_stage.v"
click node_exmem "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/ex_mem.v"
click node_memory_stage "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/mem_stage.v"
click node_memwb "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/mem_wb.v"
click node_writeback "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/wb_stage.v"
click node_alu "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/alu.v"
click node_register_file "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/register_file.v"
click node_hazards "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/hazard_detection.v"
click node_forwarding "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/forwarding_unit.v"
click node_instruction_cache "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/instruction_cache.v"
click node_data_cache "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/data_cache.v"
click node_cache_control "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/cache_controller.v"
click node_cache_refill "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/cache_refill.v"
click node_branch_predictor "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/branch_predictor.v"
click node_branch_stats "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/branch_stats.v"
click node_cpi_monitor "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/cpi_monitor.v"
click node_cache_monitor "https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/cache_monitor.v"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_processor,node_fetch,node_ifid,node_idex,node_exmem,node_memwb,node_writeback toneBlue
class node_decode,node_execute,node_alu,node_register_file,node_hazards,node_forwarding toneAmber
class node_memory_stage,node_instruction_cache,node_data_cache,node_cache_control,node_cache_refill toneMint
class node_branch_predictor,node_branch_stats toneRose
class node_cpi_monitor,node_cache_monitor,node_workload toneIndigo
```

## Components

### Pipeline

- [Processor top](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/rv32i_pipeline_top.v): `rv32i_pipeline_top.v`
- [Instruction fetch](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/if_stage.v): `if_stage.v`
- [IF/ID register](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/if_id.v): `if_id.v`
- [ID/EX register](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/id_ex.v): `id_ex.v`
- [EX/MEM register](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/ex_mem.v): `ex_mem.v`
- [MEM/WB register](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/mem_wb.v): `mem_wb.v`
- [Write-back stage](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/wb_stage.v): `wb_stage.v`

### Decode and Execute

- [Instruction decode](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/id_stage.v): `id_stage.v`
- [Execute stage](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/ex_stage.v): `ex_stage.v`
- [ALU and control](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/alu.v): `alu.v`
- [Register file](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/register_file.v): `register_file.v`
- [Hazard detection](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/hazard_detection.v): `hazard_detection.v`
- [Data forwarding](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/forwarding_unit.v): `forwarding_unit.v`

### Memory System

- [Memory stage](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/mem_stage.v): `mem_stage.v`
- [Instruction cache](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/instruction_cache.v): `instruction_cache.v`
- [Data cache](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/data_cache.v): `data_cache.v`
- [Cache controller](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/cache_controller.v): `cache_controller.v`
- [Cache refill](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/cache_refill.v): `cache_refill.v`

### Branch Control

- [Branch predictor](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/branch_predictor.v): `branch_predictor.v`
- [Branch statistics](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/branch_stats.v): `branch_stats.v`

### Performance Monitoring

- [CPI monitor](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/cpi_monitor.v): `cpi_monitor.v`
- [Cache monitor](https://github.com/sneha-prathipati/rv32i-pipelined-risc-v-processor/blob/main/cache_monitor.v): `cache_monitor.v`

### Other components

- **Instruction workload**

## Connections

- Instruction workload → Processor top: provides instructions
- Processor top → Instruction fetch: starts pipeline
- Instruction fetch → IF/ID register: passes fetched instruction
- IF/ID register → Instruction decode: passes instruction
- Instruction decode → ID/EX register: passes decoded values
- ID/EX register → Execute stage: passes operands
- Execute stage → EX/MEM register: passes results
- EX/MEM register → Memory stage: passes memory operation
- Memory stage → MEM/WB register: passes result
- MEM/WB register → Write-back stage: passes result
- Instruction fetch → Instruction cache: fetches instructions
- Memory stage → Data cache: accesses data
- Instruction decode → Register file: reads registers
- Write-back stage → Register file: writes registers
- Execute stage → ALU and control: computes operations
- Hazard detection → Processor top: controls stalls and flushes
- Data forwarding → Execute stage: forwards operands
- Branch predictor → Branch statistics: records predictions