How s-steven-joshua/amba_ahb_lite works
This repository implements an AHB-Lite master/slave system and documents focused verification of transfers, bursts, and error handling. The README establishes the system-level interactions and test coverage; no RTL or testbench source excerpts were provided, so internal call details and the role of ahb_top are not inferred.
Main entry points: ahb_master_lite.sv AHB Master · ahb_slave.sv AHB Slave · ahb_top.sv AHB Top · tb.sv Single Transfers
Components 13
Master Engine
- AHB Master
RTL/ahb_master_lite.sv - AHB Top
RTL/ahb_top.sv
Slave and Memory
- AHB Slave
RTL/ahb_slave.sv - Memory RAM
Protocol Verification
- Single Transfers
Testbench/Single Write and Single Read for different Hsize/tb.sv - Increment Bursts
Testbench/INCR 16/tb.sv - Undefined INCR
Testbench/Undefined INCR write and read/tb.sv - Early Termination
Testbench/Early termination of burst in undefined INCR /tb.sv - Wrap Bursts
Testbench/Wrap 8/tb.sv - BUSY Transfer
Testbench/wrap 4 with busy state/tb.sv - Alignment Check
Testbench/Unaligned address/tb.sv - Range Errors
Testbench/Address out of range/tb.sv
Other components
- Testbench Stimulus
Connections 13
- Testbench Stimulus → AHB Master: drives stimulus
README.md - AHB Master → AHB Slave: sends AHB-Lite bus
README.md - AHB Slave → Memory RAM: reads and writes
README.md - Single Transfers → AHB Master: tests transfers
README.md - Increment Bursts → AHB Master: tests bursts
README.md - Undefined INCR → AHB Master: tests bursts
README.md - Early Termination → AHB Master: tests termination
README.md - Wrap Bursts → AHB Master: tests wrapping
README.md - BUSY Transfer → AHB Master: tests BUSY cycles
README.md - Alignment Check → AHB Slave: tests alignment
README.md - Range Errors → AHB Slave: tests error response
README.md - AHB Top → AHB Master
- AHB Top → AHB Slave