# s-steven-joshua/amba_ahb_lite architecture

> Architecture diagram of the GitHub repository s-steven-joshua/amba_ahb_lite, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-30). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/s-steven-joshua/amba_ahb_lite
- Repository: https://github.com/s-steven-joshua/amba_ahb_lite

## Overview

This repository implements an AHB-Lite master/slave system and documents focused verification of transfers, bursts, and error handling. The README establishes the system-level interactions and test coverage; no RTL or testbench source excerpts were provided, so internal call details and the role of ahb_top are not inferred.

Main entry points: [`RTL/ahb_master_lite.sv`](https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/RTL/ahb_master_lite.sv) (AHB Master), [`RTL/ahb_slave.sv`](https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/RTL/ahb_slave.sv) (AHB Slave), [`RTL/ahb_top.sv`](https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/RTL/ahb_top.sv) (AHB Top), [`Testbench/Single Write and Single Read for different Hsize/tb.sv`](https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/Testbench/Single%20Write%20and%20Single%20Read%20for%20different%20Hsize/tb.sv) (Single Transfers)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_master["Master Engine"]
  node_master["AHB Master<br/>[ahb_master_lite.sv]"]
  node_top["AHB Top<br/>[ahb_top.sv]"]
end

subgraph group_slave["Slave and Memory"]
  node_slave["AHB Slave<br/>[ahb_slave.sv]"]
  node_ram[("Memory RAM")]
end

subgraph group_verification["Protocol Verification"]
  node_single_test["Single Transfers<br/>[tb.sv]"]
  node_increment_test["Increment Bursts<br/>[tb.sv]"]
  node_undefined_test["Undefined INCR<br/>[tb.sv]"]
  node_early_test["Early Termination<br/>[tb.sv]"]
  node_wrap_test["Wrap Bursts<br/>[tb.sv]"]
  node_busy_test["BUSY Transfer<br/>[tb.sv]"]
  node_alignment_test["Alignment Check<br/>[tb.sv]"]
  node_range_test["Range Errors<br/>[tb.sv]"]
end

node_testbench_actor(("Testbench Stimulus"))

node_testbench_actor -->|"drives stimulus"| node_master
node_master -->|"sends AHB-Lite bus"| node_slave
node_slave -->|"reads and writes"| node_ram
node_single_test -->|"tests transfers"| node_master
node_increment_test -->|"tests bursts"| node_master
node_undefined_test -->|"tests bursts"| node_master
node_early_test -->|"tests termination"| node_master
node_wrap_test -->|"tests wrapping"| node_master
node_busy_test -->|"tests BUSY cycles"| node_master
node_alignment_test -->|"tests alignment"| node_slave
node_range_test -->|"tests error response"| node_slave
node_top -.-> node_master
node_top -.-> node_slave

click node_master "https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/RTL/ahb_master_lite.sv"
click node_top "https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/RTL/ahb_top.sv"
click node_slave "https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/RTL/ahb_slave.sv"
click node_single_test "https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/Testbench/Single%20Write%20and%20Single%20Read%20for%20different%20Hsize/tb.sv"
click node_increment_test "https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/Testbench/INCR%2016/tb.sv"
click node_undefined_test "https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/Testbench/Undefined%20INCR%20write%20and%20read/tb.sv"
click node_early_test "https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/Testbench/Early%20termination%20of%20burst%20in%20undefined%20INCR%20/tb.sv"
click node_wrap_test "https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/Testbench/Wrap%208/tb.sv"
click node_busy_test "https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/Testbench/wrap%204%20with%20busy%20state/tb.sv"
click node_alignment_test "https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/Testbench/Unaligned%20address/tb.sv"
click node_range_test "https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/Testbench/Address%20out%20of%20range/tb.sv"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_master,node_top toneBlue
class node_slave,node_ram toneAmber
class node_single_test,node_increment_test,node_undefined_test,node_early_test,node_wrap_test,node_busy_test,node_alignment_test,node_range_test toneMint
class node_testbench_actor toneIndigo
```

## Components

### Master Engine

- [AHB Master](https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/RTL/ahb_master_lite.sv): `RTL/ahb_master_lite.sv`
- [AHB Top](https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/RTL/ahb_top.sv): `RTL/ahb_top.sv`

### Slave and Memory

- [AHB Slave](https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/RTL/ahb_slave.sv): `RTL/ahb_slave.sv`
- **Memory RAM**

### Protocol Verification

- [Single Transfers](https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/Testbench/Single%20Write%20and%20Single%20Read%20for%20different%20Hsize/tb.sv): `Testbench/Single Write and Single Read for different Hsize/tb.sv`
- [Increment Bursts](https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/Testbench/INCR%2016/tb.sv): `Testbench/INCR 16/tb.sv`
- [Undefined INCR](https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/Testbench/Undefined%20INCR%20write%20and%20read/tb.sv): `Testbench/Undefined INCR write and read/tb.sv`
- [Early Termination](https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/Testbench/Early%20termination%20of%20burst%20in%20undefined%20INCR%20/tb.sv): `Testbench/Early termination of burst in undefined INCR /tb.sv`
- [Wrap Bursts](https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/Testbench/Wrap%208/tb.sv): `Testbench/Wrap 8/tb.sv`
- [BUSY Transfer](https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/Testbench/wrap%204%20with%20busy%20state/tb.sv): `Testbench/wrap 4 with busy state/tb.sv`
- [Alignment Check](https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/Testbench/Unaligned%20address/tb.sv): `Testbench/Unaligned address/tb.sv`
- [Range Errors](https://github.com/s-steven-joshua/amba_ahb_lite/blob/main/Testbench/Address%20out%20of%20range/tb.sv): `Testbench/Address out of range/tb.sv`

### Other components

- **Testbench Stimulus**

## Connections

- Testbench Stimulus → AHB Master: drives stimulus (evidence: `README.md`)
- AHB Master → AHB Slave: sends AHB-Lite bus (evidence: `README.md`)
- AHB Slave → Memory RAM: reads and writes (evidence: `README.md`)
- Single Transfers → AHB Master: tests transfers (evidence: `README.md`)
- Increment Bursts → AHB Master: tests bursts (evidence: `README.md`)
- Undefined INCR → AHB Master: tests bursts (evidence: `README.md`)
- Early Termination → AHB Master: tests termination (evidence: `README.md`)
- Wrap Bursts → AHB Master: tests wrapping (evidence: `README.md`)
- BUSY Transfer → AHB Master: tests BUSY cycles (evidence: `README.md`)
- Alignment Check → AHB Slave: tests alignment (evidence: `README.md`)
- Range Errors → AHB Slave: tests error response (evidence: `README.md`)
- AHB Top → AHB Master
- AHB Top → AHB Slave