How mohamedhussein27/fifo-uvm works
This repository pairs a synchronous FIFO RTL design with a UVM verification environment. The documented workflow starts at the test, initializes the environment, runs reset and read/write stimulus through the driver and interface, then observes DUT behavior for scoreboard comparison and functional coverage; assertions check protocol behavior throughout. The graph preserves the documented verification stages and major components. Source excerpts were unavailable, so relationships are limited to those stated in the README; implementation details and some connections remain unverified.
Main entry points: FIFO_DRIVER.sv Driver · FIFO_MONITOR.sv Monitor · FIFO_ENV.sv UVM Environment · FIFO_IF.sv FIFO Interface
Components 20
FIFO Design
- Synchronous FIFO
UVM Based Verification/FIFO.sv
Stimulus Generation
- Sequence Item
UVM Based Verification/FIFO_SEQUENCE_ITEM.sv - Sequencer
UVM Based Verification/FIFO_SEQUENCER.sv - Main Sequence
UVM Based Verification/FIFO_MAIN_SEQUENCE.sv - Reset Sequence
UVM Based Verification/FIFO_RESET_SEQUENCE.sv - Write Sequence
UVM Based Verification/FIFO_WRITE_SEQUENCE.sv - Read Sequence
UVM Based Verification/FIFO_READ_SEQUENCE.sv - Write-Read Sequence
UVM Based Verification/FIFO_WRITE_READ_SEQUENCE.sv - Driver
UVM Based Verification/FIFO_DRIVER.sv
Checking and Coverage
- Monitor
UVM Based Verification/FIFO_MONITOR.sv - Scoreboard
UVM Based Verification/FIFO_SCOREBOARD.sv - Coverage Collector
UVM Based Verification/FIFO_COVERAGE_COLLECTOR.sv - Protocol Assertions
UVM Based Verification/FIFO_SVA.sv
UVM Harness
- UVM Test
UVM Based Verification/FIFO_TEST.sv - UVM Environment
UVM Based Verification/FIFO_ENV.sv - Testbench Top
UVM Based Verification/FIFO_TOP.sv - Configuration
UVM Based Verification/FIFO_CONFIG.sv - UVM Agent
UVM Based Verification/FIFO_AGENT.sv - FIFO Interface
UVM Based Verification/FIFO_IF.sv
Other components
- Test Runner
Connections 15
- Test Runner → UVM Test: runs
README.md - UVM Test → UVM Environment: initiates
README.md - UVM Environment → UVM Agent: connects
README.md - UVM Environment → Configuration: applies settings
README.md - Testbench Top → FIFO Interface: connects
README.md - FIFO Interface → Synchronous FIFO: connects signals
README.md - Reset Sequence → Driver: provides stimulus
README.md - Write Sequence → Driver: provides stimulus
README.md - Read Sequence → Driver: provides stimulus
README.md - Write-Read Sequence → Driver: provides stimulus
README.md - Driver → FIFO Interface: drives signals
README.md - Monitor → Synchronous FIFO: observes behavior
README.md - Monitor → Scoreboard: samples transactions
README.md - Monitor → Coverage Collector: samples transactions
README.md - Protocol Assertions → Synchronous FIFO: checks protocol
README.md