How talhaisrar/riscv-rv32im-axi4-lite-soc works
This repository implements a pipelined RV32IM processor in an AXI4-Lite SoC. The principal workflow is instruction fetch, decode, execute, memory access, and writeback; hazard handling, forwarding, branch prediction, and the M-extension support that flow. The SoC also exposes memory-mapped peripherals through an AXI4-Lite master and interconnect. Edges below reflect the README’s documented stages and integrations; source excerpts were not provided, so internal call-level connections cannot be verified.
Main entry points: execute_stage.v Execute · axi4_lite_slave.sv AXI4-Lite Slaves · fetch_stage.v Instruction Fetch · decode_stage.v Instruction Decode
Components 18
Processor Pipeline
- Instruction Fetch
src/fetch_stage/fetch_stage.v - Instruction Decode
src/decode_stage/decode_stage.v - Execute
src/execute_stage/execute_stage.v - Memory Access
src/mem_stage/mem_stage.v - Write Back
src/writeback_stage/writeback_stage.v
Pipeline Support
- Pipeline Registers
src/pipeline_registers - Hazard Unit
src/hazard_unit.v - Forwarding Unit
src/forwarding_unit.v - Branch Target Buffer
src/branch_target_buffer/btb.v - M Extension
src/m_unit_extension/riscv_m_unit.sv
AXI4-Lite SoC
- SoC Top
src/riscv_soc_top.v - Peripheral Top
src/axi4_lite_peripheral_top.sv - AXI4-Lite Master
src/axi4_lite/axi4_lite_master.sv - AXI Interconnect
src/axi4_lite_interconnect/axi4_lite_interconnect.sv - AXI4-Lite Slaves
src/axi4_lite/axi4_lite_slave.sv
Memory and Peripherals
- Data Memory
src/peripherals/data_memory.v - LED Peripheral
src/peripherals/led.sv
Other components
- RISC-V Program
programs
Connections 15
- RISC-V Program → Instruction Fetch: loads instructions
README.md - Instruction Fetch → Instruction Decode: passes instruction
README.md - Instruction Decode → Execute: passes operands
README.md - Execute → Memory Access: passes results
README.md - Memory Access → Write Back: passes data
README.md - Hazard Unit → Pipeline Registers: controls stalls
README.md - Forwarding Unit → Execute: forwards operands
README.md - Branch Target Buffer → Instruction Fetch: predicts branches
README.md - M Extension → Execute: extends arithmetic
README.md - SoC Top → Peripheral Top: integrates peripherals
README.md - Peripheral Top → AXI4-Lite Master: connects master
README.md - AXI4-Lite Master → AXI Interconnect: issues transactions
README.md - AXI Interconnect → AXI4-Lite Slaves: routes transactions
README.md - AXI4-Lite Slaves → Data Memory: serves memory access
- AXI4-Lite Slaves → LED Peripheral: serves peripheral access