# mohamedhussein27/fifo-uvm architecture

> Architecture diagram of the GitHub repository mohamedhussein27/fifo-uvm, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-10-18). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/mohamedhussein27/fifo-uvm
- Repository: https://github.com/mohamedhussein27/fifo-uvm

## Overview

This repository pairs a synchronous FIFO RTL design with a UVM verification environment. The documented workflow starts at the test, initializes the environment, runs reset and read/write stimulus through the driver and interface, then observes DUT behavior for scoreboard comparison and functional coverage; assertions check protocol behavior throughout. The graph preserves the documented verification stages and major components. Source excerpts were unavailable, so relationships are limited to those stated in the README; implementation details and some connections remain unverified.

Main entry points: [`UVM Based Verification/FIFO_DRIVER.sv`](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_DRIVER.sv) (Driver), [`UVM Based Verification/FIFO_MONITOR.sv`](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_MONITOR.sv) (Monitor), [`UVM Based Verification/FIFO_ENV.sv`](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_ENV.sv) (UVM Environment), [`UVM Based Verification/FIFO_IF.sv`](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_IF.sv) (FIFO Interface)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_dut["FIFO Design"]
  node_dut["Synchronous FIFO<br/>[FIFO.sv]"]
end

subgraph group_stimulus["Stimulus Generation"]
  node_item["Sequence Item"]
  node_sequencer["Sequencer<br/>[FIFO_SEQUENCER.sv]"]
  node_mainseq["Main Sequence"]
  node_resetseq["Reset Sequence"]
  node_writeseq["Write Sequence"]
  node_readseq["Read Sequence"]
  node_combinedseq["Write-Read Sequence"]
  node_driver["Driver<br/>[FIFO_DRIVER.sv]"]
end

subgraph group_observe["Checking and Coverage"]
  node_monitor["Monitor<br/>[FIFO_MONITOR.sv]"]
  node_scoreboard["Scoreboard<br/>[FIFO_SCOREBOARD.sv]"]
  node_coverage["Coverage Collector"]
  node_assertions["Protocol Assertions<br/>[FIFO_SVA.sv]"]
end

subgraph group_harness["UVM Harness"]
  node_test["UVM Test<br/>[FIFO_TEST.sv]"]
  node_env["UVM Environment<br/>[FIFO_ENV.sv]"]
  node_top["Testbench Top<br/>[FIFO_TOP.sv]"]
  node_config["Configuration<br/>[FIFO_CONFIG.sv]"]
  node_agent["UVM Agent<br/>[FIFO_AGENT.sv]"]
  node_interface["FIFO Interface<br/>[FIFO_IF.sv]"]
end

node_user(("Test Runner"))

node_user -->|"runs"| node_test
node_test -->|"initiates"| node_env
node_env -->|"connects"| node_agent
node_env -->|"applies settings"| node_config
node_top -->|"connects"| node_interface
node_interface -->|"connects signals"| node_dut
node_resetseq -->|"provides stimulus"| node_driver
node_writeseq -->|"provides stimulus"| node_driver
node_readseq -->|"provides stimulus"| node_driver
node_combinedseq -->|"provides stimulus"| node_driver
node_driver -->|"drives signals"| node_interface
node_monitor -->|"observes behavior"| node_dut
node_monitor -->|"samples transactions"| node_scoreboard
node_monitor -->|"samples transactions"| node_coverage
node_assertions -->|"checks protocol"| node_dut

click node_test "https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_TEST.sv"
click node_env "https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_ENV.sv"
click node_top "https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_TOP.sv"
click node_config "https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_CONFIG.sv"
click node_agent "https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_AGENT.sv"
click node_interface "https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_IF.sv"
click node_dut "https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO.sv"
click node_item "https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_SEQUENCE_ITEM.sv"
click node_sequencer "https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_SEQUENCER.sv"
click node_mainseq "https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_MAIN_SEQUENCE.sv"
click node_resetseq "https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_RESET_SEQUENCE.sv"
click node_writeseq "https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_WRITE_SEQUENCE.sv"
click node_readseq "https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_READ_SEQUENCE.sv"
click node_combinedseq "https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_WRITE_READ_SEQUENCE.sv"
click node_driver "https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_DRIVER.sv"
click node_monitor "https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_MONITOR.sv"
click node_scoreboard "https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_SCOREBOARD.sv"
click node_coverage "https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_COVERAGE_COLLECTOR.sv"
click node_assertions "https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_SVA.sv"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_dut toneBlue
class node_item,node_sequencer,node_mainseq,node_resetseq,node_writeseq,node_readseq,node_combinedseq,node_driver toneAmber
class node_monitor,node_scoreboard,node_coverage,node_assertions toneMint
class node_test,node_env,node_top,node_config,node_agent,node_interface toneRose
class node_user toneIndigo
```

## Components

### FIFO Design

- [Synchronous FIFO](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO.sv): `UVM Based Verification/FIFO.sv`

### Stimulus Generation

- [Sequence Item](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_SEQUENCE_ITEM.sv): `UVM Based Verification/FIFO_SEQUENCE_ITEM.sv`
- [Sequencer](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_SEQUENCER.sv): `UVM Based Verification/FIFO_SEQUENCER.sv`
- [Main Sequence](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_MAIN_SEQUENCE.sv): `UVM Based Verification/FIFO_MAIN_SEQUENCE.sv`
- [Reset Sequence](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_RESET_SEQUENCE.sv): `UVM Based Verification/FIFO_RESET_SEQUENCE.sv`
- [Write Sequence](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_WRITE_SEQUENCE.sv): `UVM Based Verification/FIFO_WRITE_SEQUENCE.sv`
- [Read Sequence](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_READ_SEQUENCE.sv): `UVM Based Verification/FIFO_READ_SEQUENCE.sv`
- [Write-Read Sequence](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_WRITE_READ_SEQUENCE.sv): `UVM Based Verification/FIFO_WRITE_READ_SEQUENCE.sv`
- [Driver](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_DRIVER.sv): `UVM Based Verification/FIFO_DRIVER.sv`

### Checking and Coverage

- [Monitor](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_MONITOR.sv): `UVM Based Verification/FIFO_MONITOR.sv`
- [Scoreboard](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_SCOREBOARD.sv): `UVM Based Verification/FIFO_SCOREBOARD.sv`
- [Coverage Collector](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_COVERAGE_COLLECTOR.sv): `UVM Based Verification/FIFO_COVERAGE_COLLECTOR.sv`
- [Protocol Assertions](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_SVA.sv): `UVM Based Verification/FIFO_SVA.sv`

### UVM Harness

- [UVM Test](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_TEST.sv): `UVM Based Verification/FIFO_TEST.sv`
- [UVM Environment](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_ENV.sv): `UVM Based Verification/FIFO_ENV.sv`
- [Testbench Top](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_TOP.sv): `UVM Based Verification/FIFO_TOP.sv`
- [Configuration](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_CONFIG.sv): `UVM Based Verification/FIFO_CONFIG.sv`
- [UVM Agent](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_AGENT.sv): `UVM Based Verification/FIFO_AGENT.sv`
- [FIFO Interface](https://github.com/mohamedhussein27/fifo-uvm/blob/main/UVM%20Based%20Verification/FIFO_IF.sv): `UVM Based Verification/FIFO_IF.sv`

### Other components

- **Test Runner**

## Connections

- Test Runner → UVM Test: runs (evidence: `README.md`)
- UVM Test → UVM Environment: initiates (evidence: `README.md`)
- UVM Environment → UVM Agent: connects (evidence: `README.md`)
- UVM Environment → Configuration: applies settings (evidence: `README.md`)
- Testbench Top → FIFO Interface: connects (evidence: `README.md`)
- FIFO Interface → Synchronous FIFO: connects signals (evidence: `README.md`)
- Reset Sequence → Driver: provides stimulus (evidence: `README.md`)
- Write Sequence → Driver: provides stimulus (evidence: `README.md`)
- Read Sequence → Driver: provides stimulus (evidence: `README.md`)
- Write-Read Sequence → Driver: provides stimulus (evidence: `README.md`)
- Driver → FIFO Interface: drives signals (evidence: `README.md`)
- Monitor → Synchronous FIFO: observes behavior (evidence: `README.md`)
- Monitor → Scoreboard: samples transactions (evidence: `README.md`)
- Monitor → Coverage Collector: samples transactions (evidence: `README.md`)
- Protocol Assertions → Synchronous FIFO: checks protocol (evidence: `README.md`)