How johnh2448/hyper-fetch works
Hyper-Fetch is a parameterizable RISC-V instruction prefetcher with integrated branch prediction. Its principal workflow accepts memory responses, predicts branch direction, preprocesses instructions, queues them, and presents registered instructions in program order for the CPU to consume. The README documents a two-step preprocessing pipeline and native compressed-instruction support. The tree identifies the implementation modules, but no source excerpts were available; internal connections below reflect the documented integrated design rather than inspected call or data-transfer statements.
Main entry points: Top.sv Prefetch controller · InstructionMemory.sv Instruction memory · Predictor.sv BTFNT predictor · Queue.sv Instruction queue
Components 8
Fetch pipeline
- Prefetch controller
Source/Top.sv - Two-step preprocessing
Source/Top.sv - Compressed support
Source/Top.sv - Instruction memory
Source/InstructionMemory.sv
Branch prediction
- BTFNT predictor
Source/Predictor.sv
Instruction buffering
- Instruction queue
Source/Queue.sv
Other components
- CPU
- Cache / memory
Connections 8
- Cache / memory → Prefetch controller: sends responses
- Prefetch controller → CPU: presents instructions
- CPU → Prefetch controller: signals consumption
- Prefetch controller → BTFNT predictor: integrates prediction
- Prefetch controller → Two-step preprocessing: preprocesses fetches
- Prefetch controller → Compressed support: supports compressed
- Prefetch controller → Instruction queue: queues instructions
- Prefetch controller → Instruction memory: uses instruction memory