How jobanpreet-brar/rtl-to-gdsii-picorv32 works
This repository documents a PicoRV32 implementation from functional verification through synthesis, physical design, and timing/power analysis. The README supports the major stage relationships, but no source excerpts are available to confirm finer-grained script behavior or handoffs.
Main entry points: run_genus.tcl Genus Flow · run_innovus.tcl Innovus Flow · run_xrun.tcl Xcelium Script · run_tempus.tcl Tempus Flow
Components 14
RTL Design
- PicoRV32 Core
rtl/picorv32.v - ASIC Wrapper
rtl/asic_top.v - Timing Constraints
cons/constraints.sdc
Functional Verification
- Testbench
tb/tb_top.sv - Simulation Runner
sim/run_sim.sh - Xcelium Script
sim/run_xrun.tcl
Physical Design
- Genus Flow
synth/run_genus.tcl - Mapped Netlist
results/asic_top_netlist.v - Innovus Flow
pnr/run_innovus.tcl - Routed Layout
results/final_chip.gds
Signoff Analysis
- Parasitics
results/asic_top.spef - Tempus Flow
tempus/run_tempus.tcl - Timing Reports
tempus/tempus_summary.rpt - Power Report
pnr/power.rpt
Connections 14
- Simulation Runner → Xcelium Script: runs
- Xcelium Script → PicoRV32 Core: simulates
- Xcelium Script → ASIC Wrapper: simulates
- Xcelium Script → Testbench: runs
- Genus Flow → PicoRV32 Core: synthesizes
- Genus Flow → ASIC Wrapper: synthesizes
- Genus Flow → Timing Constraints: uses
- Genus Flow → Mapped Netlist: generates
- Innovus Flow → Mapped Netlist: implements
- Innovus Flow → Routed Layout: produces
- Innovus Flow → Parasitics: produces
- Innovus Flow → Power Report: reports
- Tempus Flow → Parasitics: analyzes
- Tempus Flow → Timing Reports: produces