How kasirga-kizil/tekno-kizil works
This repository documents the KIZIL RISC-V processor project, but the supplied tree does not include the processor RTL itself. The visible runtime-oriented material centers on bare-metal examples, processor validation and benchmark programs, plus host-side programming and simulation utilities. A typical visible workflow is to prepare firmware for a demo, load it onto a board, and observe UART output; separate validation programs exercise ISA, debug and benchmark behavior. README-described processor structure is retained as context, but its internal wiring cannot be traced from the available files. Arrows reflect only the sampled source and explicit documentation.
Main entry points: main.c UART example · tekno_example.c Bare-metal example · teknofest_ram_seri_port.py Serial programmer · uart_send_data.py UART sender
Components 19
KIZIL processor
- KIZIL CPU
- Pipeline core
- System design
Firmware examples
- UART example
testler/uart-demo/main.c - Bare-metal example
testler/baremetal-tekno-sw-edit/software/tekno_example/tekno_example.c - Peripheral drivers
testler/baremetal-tekno-sw-edit/drivers/src/uart_driver.c
Processor validation
- CoreMark benchmark
testler/coremark/core_main.c - Dhrystone benchmark
testler/dhrystone/dhry_1.c - Architecture tests
testler/riscv-arch-test/riscv-test-env/encoding.h - ISA tests
testler/riscv-tests/isa/get_static_hex.py - Debug tests
testler/riscv-tests/debug/gdbserver.py - Simulation tests
verilog-simulasyonu/testler/riscv_tests.py
Host tools
- Trace parser
testler/aapg/log_parser.py - Serial programmer
araclar/teknofest_ram_seri_port.py - UART sender
araclar/uart_programlayici/uart_send_data.py - OpenLane helper
araclar/auto_openlane.py
Other components
- Developer
- Target board
- Spike simulator
Connections 20
- Developer → UART example: runs firmware
- UART example → Peripheral drivers: uses UART
- UART example → Target board: communicates by UART
- Developer → Serial programmer: programs target
- Serial programmer → Target board: sends firmware
- Developer → UART sender: sends data
- UART sender → Target board: writes serial
- Developer → Bare-metal example: runs firmware
- Bare-metal example → Peripheral drivers: uses drivers
- Developer → CoreMark benchmark: runs benchmark
- Developer → Dhrystone benchmark: runs benchmark
- Developer → Architecture tests: runs tests
- Developer → ISA tests: runs tests
- Developer → Debug tests: runs debug tests
- Developer → Simulation tests: runs simulations
- Developer → Trace parser: parses trace
- Spike simulator → Trace parser: produces log
- Developer → OpenLane helper: invokes helper
- KIZIL CPU → Pipeline core: includes
- KIZIL CPU → System design: described by