# jobanpreet-brar/rtl-to-gdsii-picorv32 architecture

> Architecture diagram of the GitHub repository jobanpreet-brar/rtl-to-gdsii-picorv32, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-26). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/jobanpreet-brar/rtl-to-gdsii-picorv32
- Repository: https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32

## Overview

This repository documents a PicoRV32 implementation from functional verification through synthesis, physical design, and timing/power analysis. The README supports the major stage relationships, but no source excerpts are available to confirm finer-grained script behavior or handoffs.

Main entry points: [`synth/run_genus.tcl`](https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/synth/run_genus.tcl) (Genus Flow), [`pnr/run_innovus.tcl`](https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/pnr/run_innovus.tcl) (Innovus Flow), [`sim/run_xrun.tcl`](https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/sim/run_xrun.tcl) (Xcelium Script), [`tempus/run_tempus.tcl`](https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/tempus/run_tempus.tcl) (Tempus Flow)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_design["RTL Design"]
  node_core["PicoRV32 Core<br/>[picorv32.v]"]
  node_wrapper["ASIC Wrapper<br/>[asic_top.v]"]
  node_sdc["Timing Constraints<br/>[constraints.sdc]"]
end

subgraph group_verify["Functional Verification"]
  node_testbench["Testbench<br/>[tb_top.sv]"]
  node_simscript["Simulation Runner<br/>[run_sim.sh]"]
  node_xrun["Xcelium Script<br/>[run_xrun.tcl]"]
end

subgraph group_physical["Physical Design"]
  node_synthscript["Genus Flow<br/>[run_genus.tcl]"]
  node_netlist["Mapped Netlist<br/>[asic_top_netlist.v]"]
  node_innovus["Innovus Flow<br/>[run_innovus.tcl]"]
  node_layout["Routed Layout<br/>[final_chip.gds]"]
end

subgraph group_analysis["Signoff Analysis"]
  node_spef["Parasitics<br/>[asic_top.spef]"]
  node_tempus["Tempus Flow<br/>[run_tempus.tcl]"]
  node_timing["Timing Reports<br/>[tempus_summary.rpt]"]
  node_power["Power Report<br/>[power.rpt]"]
end

node_simscript -->|"runs"| node_xrun
node_xrun -->|"simulates"| node_core
node_xrun -->|"simulates"| node_wrapper
node_xrun -->|"runs"| node_testbench
node_synthscript -->|"synthesizes"| node_core
node_synthscript -->|"synthesizes"| node_wrapper
node_synthscript -->|"uses"| node_sdc
node_synthscript -->|"generates"| node_netlist
node_innovus -->|"implements"| node_netlist
node_innovus -->|"produces"| node_layout
node_innovus -->|"produces"| node_spef
node_innovus -->|"reports"| node_power
node_tempus -->|"analyzes"| node_spef
node_tempus -->|"produces"| node_timing

click node_core "https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/rtl/picorv32.v"
click node_wrapper "https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/rtl/asic_top.v"
click node_testbench "https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/tb/tb_top.sv"
click node_simscript "https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/sim/run_sim.sh"
click node_xrun "https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/sim/run_xrun.tcl"
click node_sdc "https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/cons/constraints.sdc"
click node_synthscript "https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/synth/run_genus.tcl"
click node_netlist "https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/results/asic_top_netlist.v"
click node_innovus "https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/pnr/run_innovus.tcl"
click node_layout "https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/results/final_chip.gds"
click node_spef "https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/results/asic_top.spef"
click node_tempus "https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/tempus/run_tempus.tcl"
click node_timing "https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/tempus/tempus_summary.rpt"
click node_power "https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/pnr/power.rpt"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_core,node_wrapper,node_sdc toneBlue
class node_testbench,node_simscript,node_xrun toneAmber
class node_synthscript,node_netlist,node_innovus,node_layout toneMint
class node_spef,node_tempus,node_timing,node_power toneRose
```

## Components

### RTL Design

- [PicoRV32 Core](https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/rtl/picorv32.v): `rtl/picorv32.v`
- [ASIC Wrapper](https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/rtl/asic_top.v): `rtl/asic_top.v`
- [Timing Constraints](https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/cons/constraints.sdc): `cons/constraints.sdc`

### Functional Verification

- [Testbench](https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/tb/tb_top.sv): `tb/tb_top.sv`
- [Simulation Runner](https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/sim/run_sim.sh): `sim/run_sim.sh`
- [Xcelium Script](https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/sim/run_xrun.tcl): `sim/run_xrun.tcl`

### Physical Design

- [Genus Flow](https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/synth/run_genus.tcl): `synth/run_genus.tcl`
- [Mapped Netlist](https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/results/asic_top_netlist.v): `results/asic_top_netlist.v`
- [Innovus Flow](https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/pnr/run_innovus.tcl): `pnr/run_innovus.tcl`
- [Routed Layout](https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/results/final_chip.gds): `results/final_chip.gds`

### Signoff Analysis

- [Parasitics](https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/results/asic_top.spef): `results/asic_top.spef`
- [Tempus Flow](https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/tempus/run_tempus.tcl): `tempus/run_tempus.tcl`
- [Timing Reports](https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/tempus/tempus_summary.rpt): `tempus/tempus_summary.rpt`
- [Power Report](https://github.com/jobanpreet-brar/rtl-to-gdsii-picorv32/blob/main/pnr/power.rpt): `pnr/power.rpt`

## Connections

- Simulation Runner → Xcelium Script: runs
- Xcelium Script → PicoRV32 Core: simulates
- Xcelium Script → ASIC Wrapper: simulates
- Xcelium Script → Testbench: runs
- Genus Flow → PicoRV32 Core: synthesizes
- Genus Flow → ASIC Wrapper: synthesizes
- Genus Flow → Timing Constraints: uses
- Genus Flow → Mapped Netlist: generates
- Innovus Flow → Mapped Netlist: implements
- Innovus Flow → Routed Layout: produces
- Innovus Flow → Parasitics: produces
- Innovus Flow → Power Report: reports
- Tempus Flow → Parasitics: analyzes
- Tempus Flow → Timing Reports: produces