How dhanraj18-art/64bit-risic-processor works
This repository appears to describe a 64-bit RISC processor in Verilog, with named modules for instruction handling, control, registers, arithmetic, and program-counter state, plus FPGA-facing and clock-divider modules. The file tree supports identifying these responsibilities, but the README and available source excerpts do not document module wiring or a user-to-result flow. Accordingly, the graph shows the apparent subsystems without speculative connections. The testbench is excluded as test infrastructure.
Components 8
Processor design
- Processor top
processor_top.v - Program counter
pc.v - Instruction memory
instruction_memory.v - Control unit
control_unit.v - Register file
register_file.v - ALU
alu.v
FPGA integration
- FPGA top
top_fpga.v - Clock divider
clock_divider.v