# dhanraj18-art/64bit-risic-processor architecture

> Architecture diagram of the GitHub repository dhanraj18-art/64bit-risic-processor, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-27). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/dhanraj18-art/64bit-risic-processor
- Repository: https://github.com/dhanraj18-art/64bit-risic-processor

## Overview

This repository appears to describe a 64-bit RISC processor in Verilog, with named modules for instruction handling, control, registers, arithmetic, and program-counter state, plus FPGA-facing and clock-divider modules. The file tree supports identifying these responsibilities, but the README and available source excerpts do not document module wiring or a user-to-result flow. Accordingly, the graph shows the apparent subsystems without speculative connections. The testbench is excluded as test infrastructure.

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_processor["Processor design"]
  node_processor_top["Processor top<br/>[processor_top.v]"]
  node_pc["Program counter<br/>[pc.v]"]
  node_instruction_memory["Instruction memory"]
  node_control_unit["Control unit<br/>[control_unit.v]"]
  node_register_file["Register file<br/>[register_file.v]"]
  node_alu["ALU<br/>[alu.v]"]
end

subgraph group_fpga["FPGA integration"]
  node_top_fpga["FPGA top<br/>[top_fpga.v]"]
  node_clock_divider["Clock divider<br/>[clock_divider.v]"]
end

click node_processor_top "https://github.com/dhanraj18-art/64bit-risic-processor/blob/main/processor_top.v"
click node_pc "https://github.com/dhanraj18-art/64bit-risic-processor/blob/main/pc.v"
click node_instruction_memory "https://github.com/dhanraj18-art/64bit-risic-processor/blob/main/instruction_memory.v"
click node_control_unit "https://github.com/dhanraj18-art/64bit-risic-processor/blob/main/control_unit.v"
click node_register_file "https://github.com/dhanraj18-art/64bit-risic-processor/blob/main/register_file.v"
click node_alu "https://github.com/dhanraj18-art/64bit-risic-processor/blob/main/alu.v"
click node_top_fpga "https://github.com/dhanraj18-art/64bit-risic-processor/blob/main/top_fpga.v"
click node_clock_divider "https://github.com/dhanraj18-art/64bit-risic-processor/blob/main/clock_divider.v"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_processor_top,node_pc,node_instruction_memory,node_control_unit,node_register_file,node_alu toneBlue
class node_top_fpga,node_clock_divider toneAmber
```

## Components

### Processor design

- [Processor top](https://github.com/dhanraj18-art/64bit-risic-processor/blob/main/processor_top.v): `processor_top.v`
- [Program counter](https://github.com/dhanraj18-art/64bit-risic-processor/blob/main/pc.v): `pc.v`
- [Instruction memory](https://github.com/dhanraj18-art/64bit-risic-processor/blob/main/instruction_memory.v): `instruction_memory.v`
- [Control unit](https://github.com/dhanraj18-art/64bit-risic-processor/blob/main/control_unit.v): `control_unit.v`
- [Register file](https://github.com/dhanraj18-art/64bit-risic-processor/blob/main/register_file.v): `register_file.v`
- [ALU](https://github.com/dhanraj18-art/64bit-risic-processor/blob/main/alu.v): `alu.v`

### FPGA integration

- [FPGA top](https://github.com/dhanraj18-art/64bit-risic-processor/blob/main/top_fpga.v): `top_fpga.v`
- [Clock divider](https://github.com/dhanraj18-art/64bit-risic-processor/blob/main/clock_divider.v): `clock_divider.v`