How gourav-ctrl/risc-v works
This repository appears to implement a RISC-V processor: its RTL filenames identify fetch, control, execution, and state modules. No README or source excerpts are available, so their wiring and the precise instruction-to-result flow cannot be verified; the graph therefore shows the named components without asserting connections. The testbench is excluded.
Components 9
Core
- RISC-V top
top_riscv.v
Instruction control
- Instruction fetch
instruction_fetch_unit.v - Instruction memory
INSTRUCTION_MEMORY.v - Control unit
control_unit.v - Immediate generator
imm_gen.v
Execution and state
- Datapath
data_path.v - ALU
alu.v - Register file
register_file.v - Data memory
data_memory.v