# ananthbhat94/ddr4memorycontroller architecture

> Architecture diagram of the GitHub repository ananthbhat94/ddr4memorycontroller, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-29). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/ananthbhat94/ddr4memorycontroller
- Repository: https://github.com/ananthbhat94/ddr4memorycontroller

## Overview

DDR4MemoryController accepts cache read/write requests carrying a 32-bit address and 64 bytes of write data, queues up to eight requests, and supports open-page policy and out-of-order execution. The documented simulation top integrates a CacheBFM and a Memory BFM. Filenames identify likely controller and DDR4-interface responsibilities, but no source excerpts were available to confirm how those modules call or connect, so the graph limits internal wiring to documented relationships.

Main entry points: [`MemoryController.sv`](https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/MemoryController.sv) (Memory controller), [`Top.sv`](https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/Top.sv) (Cache BFM)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_top["Simulation endpoints"]
  node_cache_bfm["Cache BFM<br/>[Top.sv]"]
  node_top["Simulation top<br/>[Top.sv]"]
  node_memory_bfm["Memory BFM<br/>[Top.sv]"]
end

subgraph group_control["Memory control"]
  node_controller["Memory controller"]
  node_request_queue["Request queue"]
  node_scheduler["Out-of-order scheduler<br/>[Scheduler.sv]"]
  node_controller_fsm["Controller FSM<br/>[Controller_FSM.sv]"]
  node_receive_command["Receive command<br/>[Receive_command.sv]"]
  node_send_command["Send command<br/>[Send_command.sv]"]
  node_read_data["Read data communication<br/>[Read_data_comm.sv]"]
end

subgraph group_ddr["DDR4 operations"]
  node_ddr_interface["DDR4 interface<br/>[DDR4Interface.sv]"]
  node_read_write["Read/write handling<br/>[ReadWrite.sv]"]
  node_memory["Memory model<br/>[Memory.sv]"]
  node_c2m["Cache-to-memory interface<br/>[C2MInterface.sv]"]
  node_calc_max["Timing calculation<br/>[CalcMax.sv]"]
  node_shift_reg["Shift register<br/>[ShiftReg.sv]"]
  node_timer["Timer<br/>[Timer.sv]"]
end

node_cache_bfm -->|"sends requests"| node_controller
node_controller -->|"queues requests"| node_request_queue

click node_cache_bfm "https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/Top.sv"
click node_top "https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/Top.sv"
click node_memory_bfm "https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/Top.sv"
click node_controller "https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/MemoryController.sv"
click node_request_queue "https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/MemoryController.sv"
click node_scheduler "https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/Scheduler.sv"
click node_controller_fsm "https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/Controller_FSM.sv"
click node_receive_command "https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/Receive_command.sv"
click node_send_command "https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/Send_command.sv"
click node_read_data "https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/Read_data_comm.sv"
click node_ddr_interface "https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/DDR4Interface.sv"
click node_read_write "https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/ReadWrite.sv"
click node_memory "https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/Memory.sv"
click node_c2m "https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/C2MInterface.sv"
click node_calc_max "https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/CalcMax.sv"
click node_shift_reg "https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/ShiftReg.sv"
click node_timer "https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/Timer.sv"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_cache_bfm,node_top,node_memory_bfm toneBlue
class node_controller,node_request_queue,node_scheduler,node_controller_fsm,node_receive_command,node_send_command,node_read_data toneAmber
class node_ddr_interface,node_read_write,node_memory,node_c2m,node_calc_max,node_shift_reg,node_timer toneMint
```

## Components

### Simulation endpoints

- [Cache BFM](https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/Top.sv): `Top.sv`
- [Simulation top](https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/Top.sv): `Top.sv`
- [Memory BFM](https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/Top.sv): `Top.sv`

### Memory control

- [Memory controller](https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/MemoryController.sv): `MemoryController.sv`
- [Request queue](https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/MemoryController.sv): `MemoryController.sv`
- [Out-of-order scheduler](https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/Scheduler.sv): `Scheduler.sv`
- [Controller FSM](https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/Controller_FSM.sv): `Controller_FSM.sv`
- [Receive command](https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/Receive_command.sv): `Receive_command.sv`
- [Send command](https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/Send_command.sv): `Send_command.sv`
- [Read data communication](https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/Read_data_comm.sv): `Read_data_comm.sv`

### DDR4 operations

- [DDR4 interface](https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/DDR4Interface.sv): `DDR4Interface.sv`
- [Read/write handling](https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/ReadWrite.sv): `ReadWrite.sv`
- [Memory model](https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/Memory.sv): `Memory.sv`
- [Cache-to-memory interface](https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/C2MInterface.sv): `C2MInterface.sv`
- [Timing calculation](https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/CalcMax.sv): `CalcMax.sv`
- [Shift register](https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/ShiftReg.sv): `ShiftReg.sv`
- [Timer](https://github.com/ananthbhat94/ddr4memorycontroller/blob/master/Timer.sv): `Timer.sv`

## Connections

- Cache BFM → Memory controller: sends requests
- Memory controller → Request queue: queues requests