# aignacio/axi_dma architecture

> Architecture diagram of the GitHub repository aignacio/axi_dma, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-30). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/aignacio/axi_dma
- Repository: https://github.com/aignacio/axi_dma

## Overview

AXI DMA is an RTL IP that moves data between memory and programmed source/destination descriptors. A host configures descriptors and starts or aborts work through AXI4-Lite; the DMA FSM manages descriptor processing, streamers form AXI transfers, and the AXI master interface dispatches requests while a FIFO buffers transferred data. The README documents these principal relationships and capabilities, but the RTL excerpts were not provided, so finer wiring and the roles of wrapper modules are not inferred.

Main entry points: [`rtl/dma_streamer.sv`](https://github.com/aignacio/axi_dma/blob/master/rtl/dma_streamer.sv) (Streamers), [`rtl/dma_axi_wrapper.sv`](https://github.com/aignacio/axi_dma/blob/master/rtl/dma_axi_wrapper.sv) (AXI4-Lite slave), [`rtl/dma_axi_if.sv`](https://github.com/aignacio/axi_dma/blob/master/rtl/dma_axi_if.sv) (AXI master interface), [`rtl/dma_fsm.sv`](https://github.com/aignacio/axi_dma/blob/master/rtl/dma_fsm.sv) (DMA FSM)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_control_data["Control and data path"]
  node_fsm["DMA FSM<br/>[dma_fsm.sv]"]
  node_streamers["Streamers<br/>[dma_streamer.sv]"]
  node_fifo["Data FIFO<br/>[dma_fifo.sv]"]
  node_func_wrapper["Function wrapper"]
end

subgraph group_bus_interfaces["Bus interfaces"]
  node_axi_wrapper["AXI wrapper<br/>[dma_axi_wrapper.sv]"]
  node_axi_master["AXI master interface<br/>[dma_axi_if.sv]"]
  node_axi_lite["AXI4-Lite slave<br/>[dma_axi_wrapper.sv]"]
end

subgraph group_registers["Registers"]
  node_csr_block["CSR block<br/>[csr_dma.sv]"]
end

node_host(("Host"))
node_axi_memory[("AXI memory")]

node_host -->|"programs CSRs"| node_axi_lite
node_axi_lite -.->|"accesses registers"| node_csr_block
node_fsm -->|"dispatches descriptors"| node_streamers
node_streamers -->|"requests transfers"| node_axi_master
node_axi_master -->|"reads and writes"| node_axi_memory
node_streamers -->|"buffers data"| node_fifo
node_axi_wrapper -.->|"exposes interface"| node_axi_lite

click node_fsm "https://github.com/aignacio/axi_dma/blob/master/rtl/dma_fsm.sv"
click node_streamers "https://github.com/aignacio/axi_dma/blob/master/rtl/dma_streamer.sv"
click node_fifo "https://github.com/aignacio/axi_dma/blob/master/rtl/dma_fifo.sv"
click node_func_wrapper "https://github.com/aignacio/axi_dma/blob/master/rtl/dma_func_wrapper.sv"
click node_axi_wrapper "https://github.com/aignacio/axi_dma/blob/master/rtl/dma_axi_wrapper.sv"
click node_axi_master "https://github.com/aignacio/axi_dma/blob/master/rtl/dma_axi_if.sv"
click node_csr_block "https://github.com/aignacio/axi_dma/blob/master/csr_out/csr_dma.sv"
click node_axi_lite "https://github.com/aignacio/axi_dma/blob/master/rtl/dma_axi_wrapper.sv"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_fsm,node_streamers,node_fifo,node_func_wrapper toneBlue
class node_axi_wrapper,node_axi_master,node_axi_lite,node_axi_memory toneAmber
class node_csr_block toneMint
class node_host toneIndigo
```

## Components

### Control and data path

- [DMA FSM](https://github.com/aignacio/axi_dma/blob/master/rtl/dma_fsm.sv): `rtl/dma_fsm.sv`
- [Streamers](https://github.com/aignacio/axi_dma/blob/master/rtl/dma_streamer.sv): `rtl/dma_streamer.sv`
- [Data FIFO](https://github.com/aignacio/axi_dma/blob/master/rtl/dma_fifo.sv): `rtl/dma_fifo.sv`
- [Function wrapper](https://github.com/aignacio/axi_dma/blob/master/rtl/dma_func_wrapper.sv): `rtl/dma_func_wrapper.sv`

### Bus interfaces

- [AXI wrapper](https://github.com/aignacio/axi_dma/blob/master/rtl/dma_axi_wrapper.sv): `rtl/dma_axi_wrapper.sv`
- [AXI master interface](https://github.com/aignacio/axi_dma/blob/master/rtl/dma_axi_if.sv): `rtl/dma_axi_if.sv`
- [AXI4-Lite slave](https://github.com/aignacio/axi_dma/blob/master/rtl/dma_axi_wrapper.sv): `rtl/dma_axi_wrapper.sv`

### Registers

- [CSR block](https://github.com/aignacio/axi_dma/blob/master/csr_out/csr_dma.sv): `csr_out/csr_dma.sv`

### Other components

- **Host**
- **AXI memory**

## Connections

- Host → AXI4-Lite slave: programs CSRs (evidence: `README.md`)
- AXI4-Lite slave → CSR block: accesses registers
- DMA FSM → Streamers: dispatches descriptors (evidence: `README.md`)
- Streamers → AXI master interface: requests transfers (evidence: `README.md`)
- AXI master interface → AXI memory: reads and writes (evidence: `README.md`)
- Streamers → Data FIFO: buffers data (evidence: `README.md`)
- AXI wrapper → AXI4-Lite slave: exposes interface