How xilinx/vitis-hls-introductory-examples works
This repository is a catalog of independent, synthesizable C/C++ examples for AMD Vitis HLS, not a single application. An engineer selects an example, studies its kernel and HLS technique, and can use the documented Vitis flow to run simulation, synthesis, and co-simulation. The major branches cover DSP, array partitioning, interfaces and memory, C/C++ modeling, pipelining, task-level parallelism, and RTL blackboxing. The graph groups representative examples by topic; sampled source confirms only a subset of their implementations, so it does not imply shared runtime wiring.
Main entry points: fft FFT variants · decimator FIR filters · array_partition_complete Complete partition · Memory Memory interfaces
Components 20
DSP examples
- FFT variants
DSP/fft - FIR filters
DSP/fir/decimator - Intrinsic FIR
DSP/DSP_Intrinsic_Library
Array partitioning
- Complete partition
Array/array_partition_complete - Block-cyclic partition
Array/array_partition_block_cyclic - Partition library
Array/array_partition_lib_simple
Interfaces and memory
- Memory interfaces
Interface/Memory - Streaming interfaces
Interface/Streaming - Register interfaces
Interface/Register - Port aggregation
Interface/Aggregation_Disaggregation
C/C++ modeling
- Pointer modeling
Modeling/Pointers - Numeric types
Modeling/using_arbitrary_precision_arith - Array stencils
Modeling/using_array_stencil_2d - Fixed-point square root
Modeling/fixed_point_sqrt
Parallel execution
- Loop pipelining
Pipelining/Loops/pipelined_loop - Task channels
Task_level_Parallelism/Control_driven/Channels - Task interfaces
Task_level_Parallelism/Data_driven
RTL integration
- RTL blackbox
Misc/rtl_as_blackbox
Other components
- HLS engineer
- Vitis HLS flow
Connections 26
- HLS engineer → FFT variants: studies example
- HLS engineer → FIR filters: studies example
- HLS engineer → Intrinsic FIR: studies example
- HLS engineer → Complete partition: studies example
- HLS engineer → Block-cyclic partition: studies example
- HLS engineer → Partition library: studies example
- HLS engineer → Memory interfaces: studies example
- HLS engineer → Streaming interfaces: studies example
- HLS engineer → Register interfaces: studies example
- HLS engineer → Port aggregation: studies example
- HLS engineer → Pointer modeling: studies example
- HLS engineer → Numeric types: studies example
- HLS engineer → Array stencils: studies example
- HLS engineer → Fixed-point square root: studies example
- HLS engineer → Loop pipelining: studies example
- HLS engineer → Task channels: studies example
- HLS engineer → Task interfaces: studies example
- HLS engineer → RTL blackbox: studies example
- FFT variants → Vitis HLS flow: demonstrates HLS use
- FIR filters → Vitis HLS flow: demonstrates HLS use
- Complete partition → Vitis HLS flow: demonstrates HLS use
- Memory interfaces → Vitis HLS flow: demonstrates HLS use
- Array stencils → Vitis HLS flow: demonstrates HLS use
- Loop pipelining → Vitis HLS flow: demonstrates HLS use
- Task channels → Vitis HLS flow: demonstrates HLS use
- RTL blackbox → Vitis HLS flow: demonstrates HLS use