# xilinx/vitis-hls-introductory-examples architecture

> Architecture diagram of the GitHub repository xilinx/vitis-hls-introductory-examples, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-26). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/xilinx/vitis-hls-introductory-examples
- Repository: https://github.com/xilinx/vitis-hls-introductory-examples

## Overview

This repository is a catalog of independent, synthesizable C/C++ examples for AMD Vitis HLS, not a single application. An engineer selects an example, studies its kernel and HLS technique, and can use the documented Vitis flow to run simulation, synthesis, and co-simulation. The major branches cover DSP, array partitioning, interfaces and memory, C/C++ modeling, pipelining, task-level parallelism, and RTL blackboxing. The graph groups representative examples by topic; sampled source confirms only a subset of their implementations, so it does not imply shared runtime wiring.

Main entry points: [`DSP/fft`](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/DSP/fft) (FFT variants), [`DSP/fir/decimator`](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/DSP/fir/decimator) (FIR filters), [`Array/array_partition_complete`](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Array/array_partition_complete) (Complete partition), [`Interface/Memory`](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Interface/Memory) (Memory interfaces)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_dsp["DSP examples"]
  node_fft["FFT variants"]
  node_fir["FIR filters"]
  node_intrinsic_fir["Intrinsic FIR"]
end

subgraph group_array["Array partitioning"]
  node_partition_complete["Complete partition"]
  node_partition_cyclic["Block-cyclic partition"]
  node_partition_lib["Partition library"]
end

subgraph group_interfaces["Interfaces and memory"]
  node_memory["Memory interfaces"]
  node_streaming["Streaming interfaces"]
  node_register["Register interfaces"]
  node_aggregation["Port aggregation"]
end

subgraph group_modeling["C/C++ modeling"]
  node_pointers["Pointer modeling"]
  node_precision["Numeric types"]
  node_stencils["Array stencils"]
  node_fixed_sqrt["Fixed-point square root"]
end

subgraph group_parallel["Parallel execution"]
  node_pipelining["Loop pipelining"]
  node_channels["Task channels"]
  node_task_modes["Task interfaces"]
end

subgraph group_misc["RTL integration"]
  node_rtl_blackbox["RTL blackbox"]
end

node_engineer(("HLS engineer"))
node_hls_flow["Vitis HLS flow"]

node_engineer -->|"studies example"| node_fft
node_engineer -->|"studies example"| node_fir
node_engineer -->|"studies example"| node_intrinsic_fir
node_engineer -->|"studies example"| node_partition_complete
node_engineer -->|"studies example"| node_partition_cyclic
node_engineer -->|"studies example"| node_partition_lib
node_engineer -->|"studies example"| node_memory
node_engineer -->|"studies example"| node_streaming
node_engineer -->|"studies example"| node_register
node_engineer -->|"studies example"| node_aggregation
node_engineer -->|"studies example"| node_pointers
node_engineer -->|"studies example"| node_precision
node_engineer -->|"studies example"| node_stencils
node_engineer -->|"studies example"| node_fixed_sqrt
node_engineer -->|"studies example"| node_pipelining
node_engineer -->|"studies example"| node_channels
node_engineer -->|"studies example"| node_task_modes
node_engineer -->|"studies example"| node_rtl_blackbox
node_fft -.->|"demonstrates HLS use"| node_hls_flow
node_fir -.->|"demonstrates HLS use"| node_hls_flow
node_partition_complete -.->|"demonstrates HLS use"| node_hls_flow
node_memory -.->|"demonstrates HLS use"| node_hls_flow
node_stencils -.->|"demonstrates HLS use"| node_hls_flow
node_pipelining -.->|"demonstrates HLS use"| node_hls_flow
node_channels -.->|"demonstrates HLS use"| node_hls_flow
node_rtl_blackbox -.->|"demonstrates HLS use"| node_hls_flow

click node_fft "https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/DSP/fft"
click node_fir "https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/DSP/fir/decimator"
click node_intrinsic_fir "https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/DSP/DSP_Intrinsic_Library"
click node_partition_complete "https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Array/array_partition_complete"
click node_partition_cyclic "https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Array/array_partition_block_cyclic"
click node_partition_lib "https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Array/array_partition_lib_simple"
click node_memory "https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Interface/Memory"
click node_streaming "https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Interface/Streaming"
click node_register "https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Interface/Register"
click node_aggregation "https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Interface/Aggregation_Disaggregation"
click node_pointers "https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Modeling/Pointers"
click node_precision "https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Modeling/using_arbitrary_precision_arith"
click node_stencils "https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Modeling/using_array_stencil_2d"
click node_fixed_sqrt "https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Modeling/fixed_point_sqrt"
click node_pipelining "https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Pipelining/Loops/pipelined_loop"
click node_channels "https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Task_level_Parallelism/Control_driven/Channels"
click node_task_modes "https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Task_level_Parallelism/Data_driven"
click node_rtl_blackbox "https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Misc/rtl_as_blackbox"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_fft,node_fir,node_intrinsic_fir toneBlue
class node_partition_complete,node_partition_cyclic,node_partition_lib toneAmber
class node_memory,node_streaming,node_register,node_aggregation toneMint
class node_pointers,node_precision,node_stencils,node_fixed_sqrt toneRose
class node_pipelining,node_channels,node_task_modes,node_engineer,node_hls_flow toneIndigo
class node_rtl_blackbox toneTeal
```

## Components

### DSP examples

- [FFT variants](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/DSP/fft): `DSP/fft`
- [FIR filters](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/DSP/fir/decimator): `DSP/fir/decimator`
- [Intrinsic FIR](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/DSP/DSP_Intrinsic_Library): `DSP/DSP_Intrinsic_Library`

### Array partitioning

- [Complete partition](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Array/array_partition_complete): `Array/array_partition_complete`
- [Block-cyclic partition](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Array/array_partition_block_cyclic): `Array/array_partition_block_cyclic`
- [Partition library](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Array/array_partition_lib_simple): `Array/array_partition_lib_simple`

### Interfaces and memory

- [Memory interfaces](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Interface/Memory): `Interface/Memory`
- [Streaming interfaces](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Interface/Streaming): `Interface/Streaming`
- [Register interfaces](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Interface/Register): `Interface/Register`
- [Port aggregation](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Interface/Aggregation_Disaggregation): `Interface/Aggregation_Disaggregation`

### C/C++ modeling

- [Pointer modeling](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Modeling/Pointers): `Modeling/Pointers`
- [Numeric types](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Modeling/using_arbitrary_precision_arith): `Modeling/using_arbitrary_precision_arith`
- [Array stencils](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Modeling/using_array_stencil_2d): `Modeling/using_array_stencil_2d`
- [Fixed-point square root](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Modeling/fixed_point_sqrt): `Modeling/fixed_point_sqrt`

### Parallel execution

- [Loop pipelining](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Pipelining/Loops/pipelined_loop): `Pipelining/Loops/pipelined_loop`
- [Task channels](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Task_level_Parallelism/Control_driven/Channels): `Task_level_Parallelism/Control_driven/Channels`
- [Task interfaces](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Task_level_Parallelism/Data_driven): `Task_level_Parallelism/Data_driven`

### RTL integration

- [RTL blackbox](https://github.com/xilinx/vitis-hls-introductory-examples/tree/master/Misc/rtl_as_blackbox): `Misc/rtl_as_blackbox`

### Other components

- **HLS engineer**
- **Vitis HLS flow**

## Connections

- HLS engineer → FFT variants: studies example
- HLS engineer → FIR filters: studies example
- HLS engineer → Intrinsic FIR: studies example
- HLS engineer → Complete partition: studies example
- HLS engineer → Block-cyclic partition: studies example
- HLS engineer → Partition library: studies example
- HLS engineer → Memory interfaces: studies example
- HLS engineer → Streaming interfaces: studies example
- HLS engineer → Register interfaces: studies example
- HLS engineer → Port aggregation: studies example
- HLS engineer → Pointer modeling: studies example
- HLS engineer → Numeric types: studies example
- HLS engineer → Array stencils: studies example
- HLS engineer → Fixed-point square root: studies example
- HLS engineer → Loop pipelining: studies example
- HLS engineer → Task channels: studies example
- HLS engineer → Task interfaces: studies example
- HLS engineer → RTL blackbox: studies example
- FFT variants → Vitis HLS flow: demonstrates HLS use
- FIR filters → Vitis HLS flow: demonstrates HLS use
- Complete partition → Vitis HLS flow: demonstrates HLS use
- Memory interfaces → Vitis HLS flow: demonstrates HLS use
- Array stencils → Vitis HLS flow: demonstrates HLS use
- Loop pipelining → Vitis HLS flow: demonstrates HLS use
- Task channels → Vitis HLS flow: demonstrates HLS use
- RTL blackbox → Vitis HLS flow: demonstrates HLS use