How vinwei2014/svpwm-foc-on-fpga works
This repository appears to be an FPGA-based SVPWM/FOC design, with modules for sine lookup, phase-vector generation, and PWM output shaping. The tree also shows a Python sine-table generator. The principal inferred workflow is a modulation design producing phase PWM signals, potentially shaped into complementary outputs. Core HDL source and a README were not sampled, so module wiring and signal behavior cannot be confirmed; the graph leaves those relationships out.
Components 7
Modulation
- SVPWM
SVPWM_FOC.srcs/sources_1/new/SVPWM.v - Phase Vector
SVPWM_FOC.srcs/sources_1/new/phase_vector_generator.v
PWM Outputs
- Phase PWM
SVPWM_FOC.srcs/sources_1/new/phase_pwm.v - CAPWM
SVPWM_FOC.srcs/sources_1/new/capwm.v - Complementary PWM
SVPWM_FOC.srcs/sources_1/new/complimentary_capwm.v
Sine Table
- Sine Lookup
SVPWM_FOC.srcs/sources_1/new/sine_lut.v - LUT Generator
sine gen/sine_lut_gen.py