# vinwei2014/svpwm-foc-on-fpga architecture

> Architecture diagram of the GitHub repository vinwei2014/svpwm-foc-on-fpga, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-28). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/vinwei2014/svpwm-foc-on-fpga
- Repository: https://github.com/vinwei2014/svpwm-foc-on-fpga

## Overview

This repository appears to be an FPGA-based SVPWM/FOC design, with modules for sine lookup, phase-vector generation, and PWM output shaping. The tree also shows a Python sine-table generator. The principal inferred workflow is a modulation design producing phase PWM signals, potentially shaped into complementary outputs. Core HDL source and a README were not sampled, so module wiring and signal behavior cannot be confirmed; the graph leaves those relationships out.

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_modulation["Modulation"]
  node_svpwm["SVPWM<br/>[SVPWM.v]"]
  node_phase_vector["Phase Vector"]
end

subgraph group_outputs["PWM Outputs"]
  node_phase_pwm["Phase PWM<br/>[phase_pwm.v]"]
  node_capwm["CAPWM<br/>[capwm.v]"]
  node_complementary_pwm["Complementary PWM"]
end

subgraph group_table["Sine Table"]
  node_sine_lut["Sine Lookup<br/>[sine_lut.v]"]
  node_lut_generator["LUT Generator<br/>[sine_lut_gen.py]"]
end

click node_svpwm "https://github.com/vinwei2014/svpwm-foc-on-fpga/blob/main/SVPWM_FOC.srcs/sources_1/new/SVPWM.v"
click node_phase_vector "https://github.com/vinwei2014/svpwm-foc-on-fpga/blob/main/SVPWM_FOC.srcs/sources_1/new/phase_vector_generator.v"
click node_sine_lut "https://github.com/vinwei2014/svpwm-foc-on-fpga/blob/main/SVPWM_FOC.srcs/sources_1/new/sine_lut.v"
click node_lut_generator "https://github.com/vinwei2014/svpwm-foc-on-fpga/blob/main/sine%20gen/sine_lut_gen.py"
click node_phase_pwm "https://github.com/vinwei2014/svpwm-foc-on-fpga/blob/main/SVPWM_FOC.srcs/sources_1/new/phase_pwm.v"
click node_capwm "https://github.com/vinwei2014/svpwm-foc-on-fpga/blob/main/SVPWM_FOC.srcs/sources_1/new/capwm.v"
click node_complementary_pwm "https://github.com/vinwei2014/svpwm-foc-on-fpga/blob/main/SVPWM_FOC.srcs/sources_1/new/complimentary_capwm.v"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_svpwm,node_phase_vector toneBlue
class node_phase_pwm,node_capwm,node_complementary_pwm toneAmber
class node_sine_lut,node_lut_generator toneMint
```

## Components

### Modulation

- [SVPWM](https://github.com/vinwei2014/svpwm-foc-on-fpga/blob/main/SVPWM_FOC.srcs/sources_1/new/SVPWM.v): `SVPWM_FOC.srcs/sources_1/new/SVPWM.v`
- [Phase Vector](https://github.com/vinwei2014/svpwm-foc-on-fpga/blob/main/SVPWM_FOC.srcs/sources_1/new/phase_vector_generator.v): `SVPWM_FOC.srcs/sources_1/new/phase_vector_generator.v`

### PWM Outputs

- [Phase PWM](https://github.com/vinwei2014/svpwm-foc-on-fpga/blob/main/SVPWM_FOC.srcs/sources_1/new/phase_pwm.v): `SVPWM_FOC.srcs/sources_1/new/phase_pwm.v`
- [CAPWM](https://github.com/vinwei2014/svpwm-foc-on-fpga/blob/main/SVPWM_FOC.srcs/sources_1/new/capwm.v): `SVPWM_FOC.srcs/sources_1/new/capwm.v`
- [Complementary PWM](https://github.com/vinwei2014/svpwm-foc-on-fpga/blob/main/SVPWM_FOC.srcs/sources_1/new/complimentary_capwm.v): `SVPWM_FOC.srcs/sources_1/new/complimentary_capwm.v`

### Sine Table

- [Sine Lookup](https://github.com/vinwei2014/svpwm-foc-on-fpga/blob/main/SVPWM_FOC.srcs/sources_1/new/sine_lut.v): `SVPWM_FOC.srcs/sources_1/new/sine_lut.v`
- [LUT Generator](https://github.com/vinwei2014/svpwm-foc-on-fpga/blob/main/sine%20gen/sine_lut_gen.py): `sine gen/sine_lut_gen.py`