How vidhyamadhavivemuri-spec/8-bit-risc-processor-design-using-verilog works
This is an educational 8-bit RISC processor RTL design. Its principal workflow is instruction fetch, opcode decode, operand access, execution or memory access, and register write-back, coordinated by the top-level CPU. The README documents these modules and datapath relationships; no source excerpts were available, so the graph follows the documented architecture and omits uncertain wiring details.
Main entry points: risc_cpu.v CPU And Program Counter · alu.v ALU · register_file.v Register File · control_unit.v Instruction Decoder
Components 6
Processor Control
- CPU And Program Counter
rtl/risc_cpu.v - Instruction Decoder
rtl/control_unit.v
Execution Datapath
- Register File
rtl/register_file.v - ALU
rtl/alu.v
Instruction And Data Memory
- Instruction Memory
rtl/instruction_memory.v - Data Memory
rtl/data_memory.v
Connections 8
- CPU And Program Counter → Instruction Memory: fetches from
- Instruction Memory → CPU And Program Counter: returns instruction
- CPU And Program Counter → Instruction Decoder: decodes opcode
- Instruction Decoder → CPU And Program Counter: generates controls
- Register File → ALU: supplies operands
- ALU → Data Memory: provides address or data
- Data Memory → Register File: returns load data
- ALU → Register File: provides result