# vidhyamadhavivemuri-spec/8-bit-risc-processor-design-using-verilog architecture

> Architecture diagram of the GitHub repository vidhyamadhavivemuri-spec/8-bit-risc-processor-design-using-verilog, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-26). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/vidhyamadhavivemuri-spec/8-bit-risc-processor-design-using-verilog
- Repository: https://github.com/vidhyamadhavivemuri-spec/8-bit-risc-processor-design-using-verilog

## Overview

This is an educational 8-bit RISC processor RTL design. Its principal workflow is instruction fetch, opcode decode, operand access, execution or memory access, and register write-back, coordinated by the top-level CPU. The README documents these modules and datapath relationships; no source excerpts were available, so the graph follows the documented architecture and omits uncertain wiring details.

Main entry points: [`rtl/risc_cpu.v`](https://github.com/vidhyamadhavivemuri-spec/8-bit-risc-processor-design-using-verilog/blob/main/rtl/risc_cpu.v) (CPU And Program Counter), [`rtl/alu.v`](https://github.com/vidhyamadhavivemuri-spec/8-bit-risc-processor-design-using-verilog/blob/main/rtl/alu.v) (ALU), [`rtl/register_file.v`](https://github.com/vidhyamadhavivemuri-spec/8-bit-risc-processor-design-using-verilog/blob/main/rtl/register_file.v) (Register File), [`rtl/control_unit.v`](https://github.com/vidhyamadhavivemuri-spec/8-bit-risc-processor-design-using-verilog/blob/main/rtl/control_unit.v) (Instruction Decoder)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_cpu["Processor Control"]
  node_risc_cpu["CPU And Program Counter<br/>[risc_cpu.v]"]
  node_control_unit["Instruction Decoder<br/>[control_unit.v]"]
end

subgraph group_datapath["Execution Datapath"]
  node_register_file[("Register File<br/>[register_file.v]")]
  node_alu["ALU<br/>[alu.v]"]
end

subgraph group_memory["Instruction And Data Memory"]
  node_instruction_memory[("Instruction Memory")]
  node_data_memory[("Data Memory<br/>[data_memory.v]")]
end

node_risc_cpu -->|"fetches from"| node_instruction_memory
node_instruction_memory -->|"returns instruction"| node_risc_cpu
node_risc_cpu -->|"decodes opcode"| node_control_unit
node_control_unit -->|"generates controls"| node_risc_cpu
node_register_file -->|"supplies operands"| node_alu
node_alu -->|"provides address or data"| node_data_memory
node_data_memory -->|"returns load data"| node_register_file
node_alu -->|"provides result"| node_register_file

click node_risc_cpu "https://github.com/vidhyamadhavivemuri-spec/8-bit-risc-processor-design-using-verilog/blob/main/rtl/risc_cpu.v"
click node_control_unit "https://github.com/vidhyamadhavivemuri-spec/8-bit-risc-processor-design-using-verilog/blob/main/rtl/control_unit.v"
click node_register_file "https://github.com/vidhyamadhavivemuri-spec/8-bit-risc-processor-design-using-verilog/blob/main/rtl/register_file.v"
click node_alu "https://github.com/vidhyamadhavivemuri-spec/8-bit-risc-processor-design-using-verilog/blob/main/rtl/alu.v"
click node_instruction_memory "https://github.com/vidhyamadhavivemuri-spec/8-bit-risc-processor-design-using-verilog/blob/main/rtl/instruction_memory.v"
click node_data_memory "https://github.com/vidhyamadhavivemuri-spec/8-bit-risc-processor-design-using-verilog/blob/main/rtl/data_memory.v"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_risc_cpu,node_control_unit toneBlue
class node_register_file,node_alu toneAmber
class node_instruction_memory,node_data_memory toneMint
```

## Components

### Processor Control

- [CPU And Program Counter](https://github.com/vidhyamadhavivemuri-spec/8-bit-risc-processor-design-using-verilog/blob/main/rtl/risc_cpu.v): `rtl/risc_cpu.v`
- [Instruction Decoder](https://github.com/vidhyamadhavivemuri-spec/8-bit-risc-processor-design-using-verilog/blob/main/rtl/control_unit.v): `rtl/control_unit.v`

### Execution Datapath

- [Register File](https://github.com/vidhyamadhavivemuri-spec/8-bit-risc-processor-design-using-verilog/blob/main/rtl/register_file.v): `rtl/register_file.v`
- [ALU](https://github.com/vidhyamadhavivemuri-spec/8-bit-risc-processor-design-using-verilog/blob/main/rtl/alu.v): `rtl/alu.v`

### Instruction And Data Memory

- [Instruction Memory](https://github.com/vidhyamadhavivemuri-spec/8-bit-risc-processor-design-using-verilog/blob/main/rtl/instruction_memory.v): `rtl/instruction_memory.v`
- [Data Memory](https://github.com/vidhyamadhavivemuri-spec/8-bit-risc-processor-design-using-verilog/blob/main/rtl/data_memory.v): `rtl/data_memory.v`

## Connections

- CPU And Program Counter → Instruction Memory: fetches from
- Instruction Memory → CPU And Program Counter: returns instruction
- CPU And Program Counter → Instruction Decoder: decodes opcode
- Instruction Decoder → CPU And Program Counter: generates controls
- Register File → ALU: supplies operands
- ALU → Data Memory: provides address or data
- Data Memory → Register File: returns load data
- ALU → Register File: provides result