varunkumar0610/risc-v-32i-5-stage-pipeline-core

How varunkumar0610/risc-v-32i-5-stage-pipeline-core works

This repository implements a five-stage pipelined RISC-V 32I processor. Its principal workflow advances instructions through fetch, decode, execution, memory access, and writeback; the README also describes pipeline registers and hazard handling with forwarding. Supporting modules cover control, arithmetic, register access, and instruction/data memories. The source excerpts were unavailable, so the graph shows only stage sequencing and hazard handling documented in the README; it does not infer internal module calls or wiring.

Main entry points: Decode_Cyle.v Instruction decode · Execute_Cycle.v Instruction execution · Memory_Cycle.v Memory access · Fetch_Cycle.v Instruction fetch

Components 18

Pipeline stages

Pipeline top src/Pipeline_Top.v
Instruction fetch src/Fetch_Cycle.v
Instruction decode src/Decode_Cyle.v
Instruction execution src/Execute_Cycle.v
Memory access src/Memory_Cycle.v
Write back src/Writeback_Cycle.v

Datapath components

ALU src/ALU.v
ALU decoder src/ALU_Decoder.v
Main decoder src/Main_Decoder.v
Control unit src/Control_Unit_Top.v
Register file src/Register_File.v
Sign extension src/Sign_Extend.v
Multiplexer src/Mux.v

Control and sequencing

Program counter src/PC.v
PC adder src/PC_Adder.v
Hazard unit src/Hazard_unit.v

Memory

Instruction memory src/Instruction_Memory.v
Data memory src/Data_Memory.v

Connections 5

Instruction fetch → Instruction decode: passes instruction README.md
Instruction decode → Instruction execution: passes decoded inputs README.md
Instruction execution → Memory access: passes result README.md
Memory access → Write back: passes memory result README.md
Hazard unit → Pipeline top: handles hazards README.md

Drawn by GitDiagram on November 13, 2026 from the repository's file tree, README and source files. Read as Markdown ·