# varunkumar0610/risc-v-32i-5-stage-pipeline-core architecture

> Architecture diagram of the GitHub repository varunkumar0610/risc-v-32i-5-stage-pipeline-core, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-11-13). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core
- Repository: https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core

## Overview

This repository implements a five-stage pipelined RISC-V 32I processor. Its principal workflow advances instructions through fetch, decode, execution, memory access, and writeback; the README also describes pipeline registers and hazard handling with forwarding. Supporting modules cover control, arithmetic, register access, and instruction/data memories. The source excerpts were unavailable, so the graph shows only stage sequencing and hazard handling documented in the README; it does not infer internal module calls or wiring.

Main entry points: [`src/Decode_Cyle.v`](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Decode_Cyle.v) (Instruction decode), [`src/Execute_Cycle.v`](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Execute_Cycle.v) (Instruction execution), [`src/Memory_Cycle.v`](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Memory_Cycle.v) (Memory access), [`src/Fetch_Cycle.v`](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Fetch_Cycle.v) (Instruction fetch)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_pipeline["Pipeline stages"]
  node_pipeline_top["Pipeline top<br/>[Pipeline_Top.v]"]
  node_fetch["Instruction fetch<br/>[Fetch_Cycle.v]"]
  node_decode["Instruction decode<br/>[Decode_Cyle.v]"]
  node_execute["Instruction execution<br/>[Execute_Cycle.v]"]
  node_memory_cycle["Memory access<br/>[Memory_Cycle.v]"]
  node_writeback["Write back<br/>[Writeback_Cycle.v]"]
end

subgraph group_datapath["Datapath components"]
  node_alu["ALU<br/>[ALU.v]"]
  node_alu_decoder["ALU decoder<br/>[ALU_Decoder.v]"]
  node_main_decoder["Main decoder<br/>[Main_Decoder.v]"]
  node_control_unit["Control unit<br/>[Control_Unit_Top.v]"]
  node_register_file[("Register file<br/>[Register_File.v]")]
  node_sign_extend["Sign extension<br/>[Sign_Extend.v]"]
  node_mux["Multiplexer<br/>[Mux.v]"]
end

subgraph group_control["Control and sequencing"]
  node_pc["Program counter<br/>[PC.v]"]
  node_pc_adder["PC adder<br/>[PC_Adder.v]"]
  node_hazard["Hazard unit<br/>[Hazard_unit.v]"]
end

subgraph group_memory["Memory"]
  node_instruction_memory[("Instruction memory")]
  node_data_memory[("Data memory<br/>[Data_Memory.v]")]
end

node_fetch -->|"passes instruction"| node_decode
node_decode -->|"passes decoded inputs"| node_execute
node_execute -->|"passes result"| node_memory_cycle
node_memory_cycle -->|"passes memory result"| node_writeback
node_hazard -->|"handles hazards"| node_pipeline_top

click node_pipeline_top "https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Pipeline_Top.v"
click node_fetch "https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Fetch_Cycle.v"
click node_decode "https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Decode_Cyle.v"
click node_execute "https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Execute_Cycle.v"
click node_memory_cycle "https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Memory_Cycle.v"
click node_writeback "https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Writeback_Cycle.v"
click node_alu "https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/ALU.v"
click node_alu_decoder "https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/ALU_Decoder.v"
click node_main_decoder "https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Main_Decoder.v"
click node_control_unit "https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Control_Unit_Top.v"
click node_register_file "https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Register_File.v"
click node_sign_extend "https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Sign_Extend.v"
click node_mux "https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Mux.v"
click node_pc "https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/PC.v"
click node_pc_adder "https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/PC_Adder.v"
click node_hazard "https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Hazard_unit.v"
click node_instruction_memory "https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Instruction_Memory.v"
click node_data_memory "https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Data_Memory.v"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_pipeline_top,node_fetch,node_decode,node_execute,node_memory_cycle,node_writeback toneBlue
class node_alu,node_alu_decoder,node_main_decoder,node_control_unit,node_register_file,node_sign_extend,node_mux toneAmber
class node_pc,node_pc_adder,node_hazard toneMint
class node_instruction_memory,node_data_memory toneRose
```

## Components

### Pipeline stages

- [Pipeline top](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Pipeline_Top.v): `src/Pipeline_Top.v`
- [Instruction fetch](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Fetch_Cycle.v): `src/Fetch_Cycle.v`
- [Instruction decode](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Decode_Cyle.v): `src/Decode_Cyle.v`
- [Instruction execution](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Execute_Cycle.v): `src/Execute_Cycle.v`
- [Memory access](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Memory_Cycle.v): `src/Memory_Cycle.v`
- [Write back](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Writeback_Cycle.v): `src/Writeback_Cycle.v`

### Datapath components

- [ALU](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/ALU.v): `src/ALU.v`
- [ALU decoder](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/ALU_Decoder.v): `src/ALU_Decoder.v`
- [Main decoder](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Main_Decoder.v): `src/Main_Decoder.v`
- [Control unit](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Control_Unit_Top.v): `src/Control_Unit_Top.v`
- [Register file](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Register_File.v): `src/Register_File.v`
- [Sign extension](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Sign_Extend.v): `src/Sign_Extend.v`
- [Multiplexer](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Mux.v): `src/Mux.v`

### Control and sequencing

- [Program counter](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/PC.v): `src/PC.v`
- [PC adder](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/PC_Adder.v): `src/PC_Adder.v`
- [Hazard unit](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Hazard_unit.v): `src/Hazard_unit.v`

### Memory

- [Instruction memory](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Instruction_Memory.v): `src/Instruction_Memory.v`
- [Data memory](https://github.com/varunkumar0610/risc-v-32i-5-stage-pipeline-core/blob/main/src/Data_Memory.v): `src/Data_Memory.v`

## Connections

- Instruction fetch → Instruction decode: passes instruction (evidence: `README.md`)
- Instruction decode → Instruction execution: passes decoded inputs (evidence: `README.md`)
- Instruction execution → Memory access: passes result (evidence: `README.md`)
- Memory access → Write back: passes memory result (evidence: `README.md`)
- Hazard unit → Pipeline top: handles hazards (evidence: `README.md`)