# talhaisrar/riscv-rv32im-axi4-lite-soc architecture

> Architecture diagram of the GitHub repository talhaisrar/riscv-rv32im-axi4-lite-soc, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-30). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/talhaisrar/riscv-rv32im-axi4-lite-soc
- Repository: https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc

## Overview

This repository implements a pipelined RV32IM processor in an AXI4-Lite SoC. The principal workflow is instruction fetch, decode, execute, memory access, and writeback; hazard handling, forwarding, branch prediction, and the M-extension support that flow. The SoC also exposes memory-mapped peripherals through an AXI4-Lite master and interconnect. Edges below reflect the README’s documented stages and integrations; source excerpts were not provided, so internal call-level connections cannot be verified.

Main entry points: [`src/execute_stage/execute_stage.v`](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/execute_stage/execute_stage.v) (Execute), [`src/axi4_lite/axi4_lite_slave.sv`](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/axi4_lite/axi4_lite_slave.sv) (AXI4-Lite Slaves), [`src/fetch_stage/fetch_stage.v`](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/fetch_stage/fetch_stage.v) (Instruction Fetch), [`src/decode_stage/decode_stage.v`](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/decode_stage/decode_stage.v) (Instruction Decode)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_core["Processor Pipeline"]
  node_fetch["Instruction Fetch<br/>[fetch_stage.v]"]
  node_decode["Instruction Decode<br/>[decode_stage.v]"]
  node_execute["Execute<br/>[execute_stage.v]"]
  node_memory["Memory Access<br/>[mem_stage.v]"]
  node_writeback["Write Back<br/>[writeback_stage.v]"]
end

subgraph group_support["Pipeline Support"]
  node_pipeline["Pipeline Registers"]
  node_hazard["Hazard Unit<br/>[hazard_unit.v]"]
  node_forwarding["Forwarding Unit<br/>[forwarding_unit.v]"]
  node_btb["Branch Target Buffer<br/>[btb.v]"]
  node_m_unit["M Extension<br/>[riscv_m_unit.sv]"]
end

subgraph group_bus["AXI4-Lite SoC"]
  node_soc["SoC Top<br/>[riscv_soc_top.v]"]
  node_axi_top["Peripheral Top"]
  node_axi_master["AXI4-Lite Master"]
  node_interconnect["AXI Interconnect"]
  node_axi_slave["AXI4-Lite Slaves<br/>[axi4_lite_slave.sv]"]
end

subgraph group_io["Memory and Peripherals"]
  node_data_memory[("Data Memory<br/>[data_memory.v]")]
  node_led["LED Peripheral<br/>[led.sv]"]
end

node_program["RISC-V Program"]

node_program -->|"loads instructions"| node_fetch
node_fetch -->|"passes instruction"| node_decode
node_decode -->|"passes operands"| node_execute
node_execute -->|"passes results"| node_memory
node_memory -->|"passes data"| node_writeback
node_hazard -->|"controls stalls"| node_pipeline
node_forwarding -->|"forwards operands"| node_execute
node_btb -->|"predicts branches"| node_fetch
node_m_unit -->|"extends arithmetic"| node_execute
node_soc -->|"integrates peripherals"| node_axi_top
node_axi_top -->|"connects master"| node_axi_master
node_axi_master -->|"issues transactions"| node_interconnect
node_interconnect -->|"routes transactions"| node_axi_slave
node_axi_slave -.->|"serves memory access"| node_data_memory
node_axi_slave -.->|"serves peripheral access"| node_led

click node_program "https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/tree/main/programs"
click node_fetch "https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/fetch_stage/fetch_stage.v"
click node_decode "https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/decode_stage/decode_stage.v"
click node_execute "https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/execute_stage/execute_stage.v"
click node_memory "https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/mem_stage/mem_stage.v"
click node_writeback "https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/writeback_stage/writeback_stage.v"
click node_pipeline "https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/tree/main/src/pipeline_registers"
click node_hazard "https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/hazard_unit.v"
click node_forwarding "https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/forwarding_unit.v"
click node_btb "https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/branch_target_buffer/btb.v"
click node_m_unit "https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/m_unit_extension/riscv_m_unit.sv"
click node_soc "https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/riscv_soc_top.v"
click node_axi_top "https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/axi4_lite_peripheral_top.sv"
click node_axi_master "https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/axi4_lite/axi4_lite_master.sv"
click node_interconnect "https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/axi4_lite_interconnect/axi4_lite_interconnect.sv"
click node_axi_slave "https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/axi4_lite/axi4_lite_slave.sv"
click node_data_memory "https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/peripherals/data_memory.v"
click node_led "https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/peripherals/led.sv"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_fetch,node_decode,node_execute,node_memory,node_writeback toneBlue
class node_pipeline,node_hazard,node_forwarding,node_btb,node_m_unit toneAmber
class node_soc,node_axi_top,node_axi_master,node_interconnect,node_axi_slave toneMint
class node_data_memory,node_led toneRose
class node_program toneTeal
```

## Components

### Processor Pipeline

- [Instruction Fetch](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/fetch_stage/fetch_stage.v): `src/fetch_stage/fetch_stage.v`
- [Instruction Decode](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/decode_stage/decode_stage.v): `src/decode_stage/decode_stage.v`
- [Execute](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/execute_stage/execute_stage.v): `src/execute_stage/execute_stage.v`
- [Memory Access](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/mem_stage/mem_stage.v): `src/mem_stage/mem_stage.v`
- [Write Back](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/writeback_stage/writeback_stage.v): `src/writeback_stage/writeback_stage.v`

### Pipeline Support

- [Pipeline Registers](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/tree/main/src/pipeline_registers): `src/pipeline_registers`
- [Hazard Unit](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/hazard_unit.v): `src/hazard_unit.v`
- [Forwarding Unit](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/forwarding_unit.v): `src/forwarding_unit.v`
- [Branch Target Buffer](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/branch_target_buffer/btb.v): `src/branch_target_buffer/btb.v`
- [M Extension](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/m_unit_extension/riscv_m_unit.sv): `src/m_unit_extension/riscv_m_unit.sv`

### AXI4-Lite SoC

- [SoC Top](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/riscv_soc_top.v): `src/riscv_soc_top.v`
- [Peripheral Top](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/axi4_lite_peripheral_top.sv): `src/axi4_lite_peripheral_top.sv`
- [AXI4-Lite Master](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/axi4_lite/axi4_lite_master.sv): `src/axi4_lite/axi4_lite_master.sv`
- [AXI Interconnect](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/axi4_lite_interconnect/axi4_lite_interconnect.sv): `src/axi4_lite_interconnect/axi4_lite_interconnect.sv`
- [AXI4-Lite Slaves](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/axi4_lite/axi4_lite_slave.sv): `src/axi4_lite/axi4_lite_slave.sv`

### Memory and Peripherals

- [Data Memory](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/peripherals/data_memory.v): `src/peripherals/data_memory.v`
- [LED Peripheral](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/blob/main/src/peripherals/led.sv): `src/peripherals/led.sv`

### Other components

- [RISC-V Program](https://github.com/talhaisrar/riscv-rv32im-axi4-lite-soc/tree/main/programs): `programs`

## Connections

- RISC-V Program → Instruction Fetch: loads instructions (evidence: `README.md`)
- Instruction Fetch → Instruction Decode: passes instruction (evidence: `README.md`)
- Instruction Decode → Execute: passes operands (evidence: `README.md`)
- Execute → Memory Access: passes results (evidence: `README.md`)
- Memory Access → Write Back: passes data (evidence: `README.md`)
- Hazard Unit → Pipeline Registers: controls stalls (evidence: `README.md`)
- Forwarding Unit → Execute: forwards operands (evidence: `README.md`)
- Branch Target Buffer → Instruction Fetch: predicts branches (evidence: `README.md`)
- M Extension → Execute: extends arithmetic (evidence: `README.md`)
- SoC Top → Peripheral Top: integrates peripherals (evidence: `README.md`)
- Peripheral Top → AXI4-Lite Master: connects master (evidence: `README.md`)
- AXI4-Lite Master → AXI Interconnect: issues transactions (evidence: `README.md`)
- AXI Interconnect → AXI4-Lite Slaves: routes transactions (evidence: `README.md`)
- AXI4-Lite Slaves → Data Memory: serves memory access
- AXI4-Lite Slaves → LED Peripheral: serves peripheral access