How skyhgzsh/loongsoncup2026 works
This repository is a submission template for a LoongArch or MIPS SoC design, not a populated SoC: the documented RTL location is empty in the supplied tree. The principal workflow is for a contestant to provide the top-level design, optional Xilinx IP, and board constraints for Vivado. The README also documents a separate assembly-program path for the final round and a location for HDL Vivado cannot directly synthesize. Vivado project-generation and implementation scripts are build tooling and are therefore not mapped; the assembly workflow is documented but its Makefiles were not sampled.
Main entry points: asm Assembly programs · soc SoC RTL · xilinx_ip Xilinx IP · constraints Board constraints
Components 10
SoC submission
- SoC RTL
src/soc - Xilinx IP
src/soc/xilinx_ip - Board constraints
run_vivado/constraints - Vivado-incompatible HDL
src/vivado_cannot
Program inputs
- Assembly programs
asm - LoongArch Makefile
asm/Makefile_la - MIPS Makefile
asm/Makefile_mips
Other components
- Contestant
- Vivado
- FPGA bitstream
Connections 11
- Contestant → SoC RTL: provides RTL
- Contestant → Xilinx IP: provides IP
- Contestant → Board constraints: provides constraints
- Contestant → Vivado-incompatible HDL: provides HDL
- Contestant → Assembly programs: writes programs
- LoongArch Makefile → Assembly programs: builds for LoongArch
- MIPS Makefile → Assembly programs: builds for MIPS
- Vivado → SoC RTL: reads RTL
- Vivado → Xilinx IP: reads IP
- Vivado → Board constraints: reads constraints
- Vivado → FPGA bitstream: produces