# skyhgzsh/loongsoncup2026 architecture

> Architecture diagram of the GitHub repository skyhgzsh/loongsoncup2026, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-29). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/skyhgzsh/loongsoncup2026
- Repository: https://github.com/skyhgzsh/loongsoncup2026

## Overview

This repository is a submission template for a LoongArch or MIPS SoC design, not a populated SoC: the documented RTL location is empty in the supplied tree. The principal workflow is for a contestant to provide the top-level design, optional Xilinx IP, and board constraints for Vivado. The README also documents a separate assembly-program path for the final round and a location for HDL Vivado cannot directly synthesize. Vivado project-generation and implementation scripts are build tooling and are therefore not mapped; the assembly workflow is documented but its Makefiles were not sampled.

Main entry points: [`asm`](https://github.com/skyhgzsh/loongsoncup2026/tree/main/asm) (Assembly programs), [`src/soc`](https://github.com/skyhgzsh/loongsoncup2026/tree/main/src/soc) (SoC RTL), [`src/soc/xilinx_ip`](https://github.com/skyhgzsh/loongsoncup2026/tree/main/src/soc/xilinx_ip) (Xilinx IP), [`run_vivado/constraints`](https://github.com/skyhgzsh/loongsoncup2026/tree/main/run_vivado/constraints) (Board constraints)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_submission["SoC submission"]
  node_rtl["SoC RTL"]
  node_ip["Xilinx IP"]
  node_constraints["Board constraints"]
  node_unsupported_hdl["Vivado-incompatible HDL"]
end

subgraph group_programming["Program inputs"]
  node_assembly["Assembly programs"]
  node_la_makefile["LoongArch Makefile"]
  node_mips_makefile["MIPS Makefile"]
end

node_contestant(("Contestant"))
node_vivado["Vivado"]
node_bitstream["FPGA bitstream"]

node_contestant -->|"provides RTL"| node_rtl
node_contestant -->|"provides IP"| node_ip
node_contestant -->|"provides constraints"| node_constraints
node_contestant -->|"provides HDL"| node_unsupported_hdl
node_contestant -->|"writes programs"| node_assembly
node_la_makefile -.->|"builds for LoongArch"| node_assembly
node_mips_makefile -.->|"builds for MIPS"| node_assembly
node_vivado -->|"reads RTL"| node_rtl
node_vivado -->|"reads IP"| node_ip
node_vivado -->|"reads constraints"| node_constraints
node_vivado -->|"produces"| node_bitstream

click node_rtl "https://github.com/skyhgzsh/loongsoncup2026/tree/main/src/soc"
click node_ip "https://github.com/skyhgzsh/loongsoncup2026/tree/main/src/soc/xilinx_ip"
click node_constraints "https://github.com/skyhgzsh/loongsoncup2026/tree/main/run_vivado/constraints"
click node_unsupported_hdl "https://github.com/skyhgzsh/loongsoncup2026/tree/main/src/vivado_cannot"
click node_assembly "https://github.com/skyhgzsh/loongsoncup2026/tree/main/asm"
click node_la_makefile "https://github.com/skyhgzsh/loongsoncup2026/blob/main/asm/Makefile_la"
click node_mips_makefile "https://github.com/skyhgzsh/loongsoncup2026/blob/main/asm/Makefile_mips"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_rtl,node_ip,node_constraints,node_unsupported_hdl toneBlue
class node_assembly,node_la_makefile,node_mips_makefile toneAmber
class node_contestant,node_vivado,node_bitstream toneIndigo
```

## Components

### SoC submission

- [SoC RTL](https://github.com/skyhgzsh/loongsoncup2026/tree/main/src/soc): `src/soc`
- [Xilinx IP](https://github.com/skyhgzsh/loongsoncup2026/tree/main/src/soc/xilinx_ip): `src/soc/xilinx_ip`
- [Board constraints](https://github.com/skyhgzsh/loongsoncup2026/tree/main/run_vivado/constraints): `run_vivado/constraints`
- [Vivado-incompatible HDL](https://github.com/skyhgzsh/loongsoncup2026/tree/main/src/vivado_cannot): `src/vivado_cannot`

### Program inputs

- [Assembly programs](https://github.com/skyhgzsh/loongsoncup2026/tree/main/asm): `asm`
- [LoongArch Makefile](https://github.com/skyhgzsh/loongsoncup2026/blob/main/asm/Makefile_la): `asm/Makefile_la`
- [MIPS Makefile](https://github.com/skyhgzsh/loongsoncup2026/blob/main/asm/Makefile_mips): `asm/Makefile_mips`

### Other components

- **Contestant**
- **Vivado**
- **FPGA bitstream**

## Connections

- Contestant → SoC RTL: provides RTL
- Contestant → Xilinx IP: provides IP
- Contestant → Board constraints: provides constraints
- Contestant → Vivado-incompatible HDL: provides HDL
- Contestant → Assembly programs: writes programs
- LoongArch Makefile → Assembly programs: builds for LoongArch
- MIPS Makefile → Assembly programs: builds for MIPS
- Vivado → SoC RTL: reads RTL
- Vivado → Xilinx IP: reads IP
- Vivado → Board constraints: reads constraints
- Vivado → FPGA bitstream: produces