How rxsaturn/sistemas-embarcados works
Purpose
This is a Sistemas Embarcados (embedded systems) course repository containing sequential weekly FPGA/digital-logic exercises, VHDL source, Quartus-style schematic designs, waveform stimuli, and supporting lecture notes. There is no README-defined application, build pipeline, or deployable service.
Hardware Design Entry Points
The practical entry points are the VHDL and block-diagram files for weeks 14–16:
• SE/Codigos VHDL_Semana 14/Codigo_01.vhd
• SE/Codigos VHDL_Semana 15/Codigo_01_simpl.vhd
• SE/Codigos VHDL - Semana 16/Codigo_decod_02.vhd
Each likely represents an independently opened/simulated hardware-design exercise rather than modules of one composed system.
Week 14 Design Stage
Week 14 provides a VHDL implementation, a corresponding schematic representation, and a waveform file for functional simulation:
• SE/Codigos VHDL_Semana 14/Codigo_01.vhd
• SE/Codigos VHDL_Semana 14/Esquematico_01.bdf
• SE/Codigos VHDL_Semana 14/Waveform_01.vwf
The .vhd source is the HDL implementation boundary; .bdf is a graphical/block-diagram design artifact; .vwf supplies test vectors or expected signal timing.
Week 15 Simplified Design Stage
Week 15 follows the same source-to-schematic-to-waveform pattern, explicitly naming the implementation as simplified:
• SE/Codigos VHDL_Semana 15/Codigo_01_simpl.vhd
• SE/Codigos VHDL_Semana 15/Esquematico_simpl_01.bdf
• SE/Codigos VHDL_Semana 15/Waveform_simpl_01.vwf
This is a separate exercise/version boundary. Do not assume its entity interfaces or behavior are compatible with Week 14 without reading the VHDL.
Week 16 Decoder Stage
Week 16 centers on a decoder-oriented VHDL design:
• SE/Codigos VHDL - Semana 16/Codigo_decod_02.vhd
• SE/Codigos VHDL - Semana 16/Proj_Decoder_01.bdf
• SE/Codigos VHDL - Semana 16/Waveform_01.vwf
The likely control flow is input signals → decoder logic → output signals, with the waveform artifact used to validate output transitions under simulated input combinations. The BDF may instantiate or visually represent the decoder design.
Simulation and Tooling Boundary
The .vhd, .bdf, and .vwf extensions indicate an FPGA/HDL workflow, plausibly Intel/Altera Quartus tooling. No project metadata, synthesis constraints, target device, board definition, runtime firmware, external API, or cloud infrastructure appears in the supplied tree. Simulation waveforms are the primary observable verification boundary.
Documentation Layer
Course material is maintained separately from executable design artifacts:
• SE/documents/Notas de Aula 14_Sistemas.md
• SE/documents/Notas de Aula 15_Sistemas.md
• SE/documents/Notas de Aula 16_Sistemas.md
Additional notes and exercise guidance span earlier and later sessions, including SE/documents/Guia_Lista_05.md and SE/documents/Notas de Aula 21_Sistemas.md. These documents provide educational context but are not invoked by the HDL designs.
Main entry points: Codigo_decod_02.vhd Decoder logic · Codigo_01.vhd VHDL implementation · Notas de Aula 14_Sistemas.md Weeks 14–16 notes · Codigo_01_simpl.vhd Simplified VHDL
Components 14
Week 14 exercise
- VHDL implementation
SE/Codigos VHDL_Semana 14/Codigo_01.vhd - Schematic design · Graphical representation of the exercise design.
SE/Codigos VHDL_Semana 14/Esquematico_01.bdf - Simulation waveform · Functional simulation vectors and timing.
SE/Codigos VHDL_Semana 14/Waveform_01.vwf
Week 15 exercise
- Simplified VHDL
SE/Codigos VHDL_Semana 15/Codigo_01_simpl.vhd - Simplified schematic
SE/Codigos VHDL_Semana 15/Esquematico_simpl_01.bdf - Simulation waveform
SE/Codigos VHDL_Semana 15/Waveform_simpl_01.vwf
Week 16 decoder
- Input signals
- Decoder logic · Decoder-oriented hardware implementation.
SE/Codigos VHDL - Semana 16/Codigo_decod_02.vhd - Output signals
- Decoder schematic
SE/Codigos VHDL - Semana 16/Proj_Decoder_01.bdf - Decoder waveform · Validates output transitions for input combinations.
SE/Codigos VHDL - Semana 16/Waveform_01.vwf
Course documentation
Educational material is separate from hardware artifacts.
- Weeks 14–16 notes · Supporting concepts for the three design exercises.
SE/documents/Notas de Aula 14_Sistemas.md - Exercise guide
SE/documents/Guia_Lista_05.md - Later lecture notes
SE/documents/Notas de Aula 21_Sistemas.md
Connections 13
- VHDL implementation → Schematic design: represented by
- Simulation waveform → VHDL implementation: simulates
- Simplified VHDL → Simplified schematic: represented by
- Simulation waveform → Simplified VHDL: simulates
- Input signals → Decoder logic: drive
- Decoder logic → Output signals: decodes to
- Decoder logic → Decoder schematic: represented by
- Decoder waveform → Input signals: provides vectors
- Decoder waveform → Output signals: checks timing
- Weeks 14–16 notes → VHDL implementation: supports
- Weeks 14–16 notes → Simplified VHDL: supports
- Weeks 14–16 notes → Decoder logic: supports
- Exercise guide → VHDL implementation: guides exercises