# rxsaturn/sistemas-embarcados architecture

> Architecture diagram of the GitHub repository rxsaturn/sistemas-embarcados, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-07-30). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/rxsaturn/sistemas-embarcados
- Repository: https://github.com/rxsaturn/sistemas-embarcados

## Overview

#### Purpose
This is a Sistemas Embarcados (embedded systems) course repository containing sequential weekly FPGA/digital-logic exercises, VHDL source, Quartus-style schematic designs, waveform stimuli, and supporting lecture notes. There is no README-defined application, build pipeline, or deployable service.

#### Hardware Design Entry Points
The practical entry points are the VHDL and block-diagram files for weeks 14–16:
- `SE/Codigos VHDL_Semana 14/Codigo_01.vhd`
- `SE/Codigos VHDL_Semana 15/Codigo_01_simpl.vhd`
- `SE/Codigos VHDL - Semana 16/Codigo_decod_02.vhd`

Each likely represents an independently opened/simulated hardware-design exercise rather than modules of one composed system.

#### Week 14 Design Stage
Week 14 provides a VHDL implementation, a corresponding schematic representation, and a waveform file for functional simulation:
- `SE/Codigos VHDL_Semana 14/Codigo_01.vhd`
- `SE/Codigos VHDL_Semana 14/Esquematico_01.bdf`
- `SE/Codigos VHDL_Semana 14/Waveform_01.vwf`

The `.vhd` source is the HDL implementation boundary; `.bdf` is a graphical/block-diagram design artifact; `.vwf` supplies test vectors or expected signal timing.

#### Week 15 Simplified Design Stage
Week 15 follows the same source-to-schematic-to-waveform pattern, explicitly naming the implementation as simplified:
- `SE/Codigos VHDL_Semana 15/Codigo_01_simpl.vhd`
- `SE/Codigos VHDL_Semana 15/Esquematico_simpl_01.bdf`
- `SE/Codigos VHDL_Semana 15/Waveform_simpl_01.vwf`

This is a separate exercise/version boundary. Do not assume its entity interfaces or behavior are compatible with Week 14 without reading the VHDL.

#### Week 16 Decoder Stage
Week 16 centers on a decoder-oriented VHDL design:
- `SE/Codigos VHDL - Semana 16/Codigo_decod_02.vhd`
- `SE/Codigos VHDL - Semana 16/Proj_Decoder_01.bdf`
- `SE/Codigos VHDL - Semana 16/Waveform_01.vwf`

The likely control flow is input signals → decoder logic → output signals, with the waveform artifact used to validate output transitions under simulated input combinations. The BDF may instantiate or visually represent the decoder design.

#### Simulation and Tooling Boundary
The `.vhd`, `.bdf`, and `.vwf` extensions indicate an FPGA/HDL workflow, plausibly Intel/Altera Quartus tooling. No project metadata, synthesis constraints, target device, board definition, runtime firmware, external API, or cloud infrastructure appears in the supplied tree. Simulation waveforms are the primary observable verification boundary.

#### Documentation Layer
Course material is maintained separately from executable design artifacts:
- `SE/documents/Notas de Aula 14_Sistemas.md`
- `SE/documents/Notas de Aula 15_Sistemas.md`
- `SE/documents/Notas de Aula 16_Sistemas.md`

Additional notes and exercise guidance span earlier and later sessions, including `SE/documents/Guia_Lista_05.md` and `SE/documents/Notas de Aula 21_Sistemas.md`. These documents provide educational context but are not invoked by the HDL designs.

Main entry points: [`SE/Codigos VHDL - Semana 16/Codigo_decod_02.vhd`](https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/Codigos%20VHDL%20-%20Semana%2016/Codigo_decod_02.vhd) (Decoder logic), [`SE/Codigos VHDL_Semana 14/Codigo_01.vhd`](https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/Codigos%20VHDL_Semana%2014/Codigo_01.vhd) (VHDL implementation), [`SE/documents/Notas de Aula 14_Sistemas.md`](https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/documents/Notas%20de%20Aula%2014_Sistemas.md) (Weeks 14–16 notes), [`SE/Codigos VHDL_Semana 15/Codigo_01_simpl.vhd`](https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/Codigos%20VHDL_Semana%2015/Codigo_01_simpl.vhd) (Simplified VHDL)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_week14["Week 14 exercise"]
  node_w14_vhdl["VHDL implementation<br/>VHDL source<br/>[Codigo_01.vhd]"]
  node_w14_bdf["Schematic design<br/>Quartus BDF<br/>[Esquematico_01.bdf]"]
  node_w14_waveform["Simulation waveform<br/>VWF stimulus<br/>[Waveform_01.vwf]"]
end

subgraph group_week15["Week 15 exercise"]
  node_w15_vhdl["Simplified VHDL<br/>VHDL source"]
  node_w15_bdf["Simplified schematic<br/>Quartus BDF"]
  node_w15_waveform["Simulation waveform<br/>VWF stimulus"]
end

subgraph group_week16["Week 16 decoder"]
  node_w16_inputs(("Input signals<br/>simulation inputs"))
  node_w16_vhdl["Decoder logic<br/>VHDL source"]
  node_w16_outputs(("Output signals<br/>simulation outputs"))
  node_w16_bdf["Decoder schematic<br/>Quartus BDF"]
  node_w16_waveform["Decoder waveform<br/>VWF stimulus<br/>[Waveform_01.vwf]"]
end

subgraph group_docs["Course documentation"]
  node_notes_14_16["Weeks 14–16 notes<br/>lecture notes"]
  node_guide_05["Exercise guide<br/>course guidance<br/>[Guia_Lista_05.md]"]
  node_notes_21["Later lecture notes"]
end

node_w14_vhdl -->|"represented by"| node_w14_bdf
node_w14_waveform -->|"simulates"| node_w14_vhdl
node_w15_vhdl -->|"represented by"| node_w15_bdf
node_w15_waveform -->|"simulates"| node_w15_vhdl
node_w16_inputs -->|"drive"| node_w16_vhdl
node_w16_vhdl -->|"decodes to"| node_w16_outputs
node_w16_vhdl -->|"represented by"| node_w16_bdf
node_w16_waveform -->|"provides vectors"| node_w16_inputs
node_w16_waveform -.->|"checks timing"| node_w16_outputs
node_notes_14_16 -.->|"supports"| node_w14_vhdl
node_notes_14_16 -.->|"supports"| node_w15_vhdl
node_notes_14_16 -.->|"supports"| node_w16_vhdl
node_guide_05 -.->|"guides exercises"| node_w14_vhdl

click node_w14_vhdl "https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/Codigos%20VHDL_Semana%2014/Codigo_01.vhd"
click node_w14_bdf "https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/Codigos%20VHDL_Semana%2014/Esquematico_01.bdf"
click node_w14_waveform "https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/Codigos%20VHDL_Semana%2014/Waveform_01.vwf"
click node_w15_vhdl "https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/Codigos%20VHDL_Semana%2015/Codigo_01_simpl.vhd"
click node_w15_bdf "https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/Codigos%20VHDL_Semana%2015/Esquematico_simpl_01.bdf"
click node_w15_waveform "https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/Codigos%20VHDL_Semana%2015/Waveform_simpl_01.vwf"
click node_w16_vhdl "https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/Codigos%20VHDL%20-%20Semana%2016/Codigo_decod_02.vhd"
click node_w16_bdf "https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/Codigos%20VHDL%20-%20Semana%2016/Proj_Decoder_01.bdf"
click node_w16_waveform "https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/Codigos%20VHDL%20-%20Semana%2016/Waveform_01.vwf"
click node_notes_14_16 "https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/documents/Notas%20de%20Aula%2014_Sistemas.md"
click node_guide_05 "https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/documents/Guia_Lista_05.md"
click node_notes_21 "https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/documents/Notas%20de%20Aula%2021_Sistemas.md"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_w14_vhdl,node_w14_bdf,node_w14_waveform toneBlue
class node_w15_vhdl,node_w15_bdf,node_w15_waveform toneAmber
class node_w16_inputs,node_w16_vhdl,node_w16_outputs,node_w16_bdf,node_w16_waveform toneMint
class node_notes_14_16,node_guide_05,node_notes_21 toneRose
```

## Components

### Week 14 exercise

- [VHDL implementation](https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/Codigos%20VHDL_Semana%2014/Codigo_01.vhd): VHDL source · `SE/Codigos VHDL_Semana 14/Codigo_01.vhd`
- [Schematic design](https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/Codigos%20VHDL_Semana%2014/Esquematico_01.bdf): Quartus BDF · Graphical representation of the exercise design. · `SE/Codigos VHDL_Semana 14/Esquematico_01.bdf`
- [Simulation waveform](https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/Codigos%20VHDL_Semana%2014/Waveform_01.vwf): VWF stimulus · Functional simulation vectors and timing. · `SE/Codigos VHDL_Semana 14/Waveform_01.vwf`

### Week 15 exercise

- [Simplified VHDL](https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/Codigos%20VHDL_Semana%2015/Codigo_01_simpl.vhd): VHDL source · `SE/Codigos VHDL_Semana 15/Codigo_01_simpl.vhd`
- [Simplified schematic](https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/Codigos%20VHDL_Semana%2015/Esquematico_simpl_01.bdf): Quartus BDF · `SE/Codigos VHDL_Semana 15/Esquematico_simpl_01.bdf`
- [Simulation waveform](https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/Codigos%20VHDL_Semana%2015/Waveform_simpl_01.vwf): VWF stimulus · `SE/Codigos VHDL_Semana 15/Waveform_simpl_01.vwf`

### Week 16 decoder

- **Input signals**: simulation inputs
- [Decoder logic](https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/Codigos%20VHDL%20-%20Semana%2016/Codigo_decod_02.vhd): VHDL source · Decoder-oriented hardware implementation. · `SE/Codigos VHDL - Semana 16/Codigo_decod_02.vhd`
- **Output signals**: simulation outputs
- [Decoder schematic](https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/Codigos%20VHDL%20-%20Semana%2016/Proj_Decoder_01.bdf): Quartus BDF · `SE/Codigos VHDL - Semana 16/Proj_Decoder_01.bdf`
- [Decoder waveform](https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/Codigos%20VHDL%20-%20Semana%2016/Waveform_01.vwf): VWF stimulus · Validates output transitions for input combinations. · `SE/Codigos VHDL - Semana 16/Waveform_01.vwf`

### Course documentation

Educational material is separate from hardware artifacts.

- [Weeks 14–16 notes](https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/documents/Notas%20de%20Aula%2014_Sistemas.md): lecture notes · Supporting concepts for the three design exercises. · `SE/documents/Notas de Aula 14_Sistemas.md`
- [Exercise guide](https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/documents/Guia_Lista_05.md): course guidance · `SE/documents/Guia_Lista_05.md`
- [Later lecture notes](https://github.com/rxsaturn/sistemas-embarcados/blob/main/SE/documents/Notas%20de%20Aula%2021_Sistemas.md): lecture notes · `SE/documents/Notas de Aula 21_Sistemas.md`

## Connections

- VHDL implementation → Schematic design: represented by
- Simulation waveform → VHDL implementation: simulates
- Simplified VHDL → Simplified schematic: represented by
- Simulation waveform → Simplified VHDL: simulates
- Input signals → Decoder logic: drive
- Decoder logic → Output signals: decodes to
- Decoder logic → Decoder schematic: represented by
- Decoder waveform → Input signals: provides vectors
- Decoder waveform → Output signals: checks timing
- Weeks 14–16 notes → VHDL implementation: supports
- Weeks 14–16 notes → Simplified VHDL: supports
- Weeks 14–16 notes → Decoder logic: supports
- Exercise guide → VHDL implementation: guides exercises