How ritu235/3-stage-pipeline works
This repository appears to be a sequence of Verilog processor-lab implementations, from individual pipeline stages to a full pipeline and FPGA-facing tops. The visible workflow is represented by those stage and integration modules; the sampled files do not show their Verilog internals, so their call and data-flow wiring is omitted. The sampled memory-image utility converts binary instruction/data images into hexadecimal files.
Main entry points: bin2hex.py Image converter · imem.bin Binary images · imem.hex Hex images
Components 16
Pipeline stages
- Fetch/decode stage
IF_ID_Stage/IF_ID.v - Execute stage
execute/execute.v - Memory stage
memory/memory.v - Writeback stage
writeback/wb.v
Pipeline integration
- Full pipeline
full_pipeline/pipeline.v - Terminal pipeline
Pipeline_via_terminal/modules/pipeline.v - IF/ID FPGA top
IF_ID_Stage/top_fpga.v - Execute FPGA top
execute/top_fpga_ex.v - Memory top
memory/top_module.v - Writeback FPGA top
writeback/top_fpga.v - Pipeline FPGA top
full_pipeline/top_fpga.v
Program images
- Binary images
Pipeline_via_terminal/mem_generator/imem_dmem/imem.bin - Image converter
Pipeline_via_terminal/mem_generator/imem_dmem/bin2hex.py - Hex images
Pipeline_via_terminal/mem_generator/imem_dmem/imem.hex - Integrated hex images
full_pipeline/imem.hex - Memory-lab hex image
memory/imem.hex
Connections 2
- Binary images → Image converter: reads
- Image converter → Hex images: writes