# ritu235/3-stage-pipeline architecture

> Architecture diagram of the GitHub repository ritu235/3-stage-pipeline, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-25). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/ritu235/3-stage-pipeline
- Repository: https://github.com/ritu235/3-stage-pipeline

## Overview

This repository appears to be a sequence of Verilog processor-lab implementations, from individual pipeline stages to a full pipeline and FPGA-facing tops. The visible workflow is represented by those stage and integration modules; the sampled files do not show their Verilog internals, so their call and data-flow wiring is omitted. The sampled memory-image utility converts binary instruction/data images into hexadecimal files.

Main entry points: [`Pipeline_via_terminal/mem_generator/imem_dmem/bin2hex.py`](https://github.com/ritu235/3-stage-pipeline/blob/main/Pipeline_via_terminal/mem_generator/imem_dmem/bin2hex.py) (Image converter), [`Pipeline_via_terminal/mem_generator/imem_dmem/imem.bin`](https://github.com/ritu235/3-stage-pipeline/blob/main/Pipeline_via_terminal/mem_generator/imem_dmem/imem.bin) (Binary images), [`Pipeline_via_terminal/mem_generator/imem_dmem/imem.hex`](https://github.com/ritu235/3-stage-pipeline/blob/main/Pipeline_via_terminal/mem_generator/imem_dmem/imem.hex) (Hex images)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_stages["Pipeline stages"]
  node_ifid["Fetch/decode stage<br/>[IF_ID.v]"]
  node_execute["Execute stage<br/>[execute.v]"]
  node_memory["Memory stage<br/>[memory.v]"]
  node_writeback["Writeback stage<br/>[wb.v]"]
end

subgraph group_integration["Pipeline integration"]
  node_fullpipe["Full pipeline<br/>[pipeline.v]"]
  node_terminalpipe["Terminal pipeline<br/>[pipeline.v]"]
  node_fpga_ifid["IF/ID FPGA top<br/>[top_fpga.v]"]
  node_fpga_execute["Execute FPGA top<br/>[top_fpga_ex.v]"]
  node_fpga_memory["Memory top<br/>[top_module.v]"]
  node_fpga_writeback["Writeback FPGA top<br/>[top_fpga.v]"]
  node_fpga_pipeline["Pipeline FPGA top<br/>[top_fpga.v]"]
end

subgraph group_images["Program images"]
  node_bin_images["Binary images<br/>[imem.bin]"]
  node_converter["Image converter<br/>[bin2hex.py]"]
  node_hex_images["Hex images<br/>[imem.hex]"]
  node_full_hex["Integrated hex images<br/>[imem.hex]"]
  node_memory_hex["Memory-lab hex image<br/>[imem.hex]"]
end

node_bin_images -->|"reads"| node_converter
node_converter -->|"writes"| node_hex_images

click node_ifid "https://github.com/ritu235/3-stage-pipeline/blob/main/IF_ID_Stage/IF_ID.v"
click node_execute "https://github.com/ritu235/3-stage-pipeline/blob/main/execute/execute.v"
click node_memory "https://github.com/ritu235/3-stage-pipeline/blob/main/memory/memory.v"
click node_writeback "https://github.com/ritu235/3-stage-pipeline/blob/main/writeback/wb.v"
click node_fullpipe "https://github.com/ritu235/3-stage-pipeline/blob/main/full_pipeline/pipeline.v"
click node_terminalpipe "https://github.com/ritu235/3-stage-pipeline/blob/main/Pipeline_via_terminal/modules/pipeline.v"
click node_fpga_ifid "https://github.com/ritu235/3-stage-pipeline/blob/main/IF_ID_Stage/top_fpga.v"
click node_fpga_execute "https://github.com/ritu235/3-stage-pipeline/blob/main/execute/top_fpga_ex.v"
click node_fpga_memory "https://github.com/ritu235/3-stage-pipeline/blob/main/memory/top_module.v"
click node_fpga_writeback "https://github.com/ritu235/3-stage-pipeline/blob/main/writeback/top_fpga.v"
click node_fpga_pipeline "https://github.com/ritu235/3-stage-pipeline/blob/main/full_pipeline/top_fpga.v"
click node_bin_images "https://github.com/ritu235/3-stage-pipeline/blob/main/Pipeline_via_terminal/mem_generator/imem_dmem/imem.bin"
click node_converter "https://github.com/ritu235/3-stage-pipeline/blob/main/Pipeline_via_terminal/mem_generator/imem_dmem/bin2hex.py"
click node_hex_images "https://github.com/ritu235/3-stage-pipeline/blob/main/Pipeline_via_terminal/mem_generator/imem_dmem/imem.hex"
click node_full_hex "https://github.com/ritu235/3-stage-pipeline/blob/main/full_pipeline/imem.hex"
click node_memory_hex "https://github.com/ritu235/3-stage-pipeline/blob/main/memory/imem.hex"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_ifid,node_execute,node_memory,node_writeback toneBlue
class node_fullpipe,node_terminalpipe,node_fpga_ifid,node_fpga_execute,node_fpga_memory,node_fpga_writeback,node_fpga_pipeline toneAmber
class node_bin_images,node_converter,node_hex_images,node_full_hex,node_memory_hex toneMint
```

## Components

### Pipeline stages

- [Fetch/decode stage](https://github.com/ritu235/3-stage-pipeline/blob/main/IF_ID_Stage/IF_ID.v): `IF_ID_Stage/IF_ID.v`
- [Execute stage](https://github.com/ritu235/3-stage-pipeline/blob/main/execute/execute.v): `execute/execute.v`
- [Memory stage](https://github.com/ritu235/3-stage-pipeline/blob/main/memory/memory.v): `memory/memory.v`
- [Writeback stage](https://github.com/ritu235/3-stage-pipeline/blob/main/writeback/wb.v): `writeback/wb.v`

### Pipeline integration

- [Full pipeline](https://github.com/ritu235/3-stage-pipeline/blob/main/full_pipeline/pipeline.v): `full_pipeline/pipeline.v`
- [Terminal pipeline](https://github.com/ritu235/3-stage-pipeline/blob/main/Pipeline_via_terminal/modules/pipeline.v): `Pipeline_via_terminal/modules/pipeline.v`
- [IF/ID FPGA top](https://github.com/ritu235/3-stage-pipeline/blob/main/IF_ID_Stage/top_fpga.v): `IF_ID_Stage/top_fpga.v`
- [Execute FPGA top](https://github.com/ritu235/3-stage-pipeline/blob/main/execute/top_fpga_ex.v): `execute/top_fpga_ex.v`
- [Memory top](https://github.com/ritu235/3-stage-pipeline/blob/main/memory/top_module.v): `memory/top_module.v`
- [Writeback FPGA top](https://github.com/ritu235/3-stage-pipeline/blob/main/writeback/top_fpga.v): `writeback/top_fpga.v`
- [Pipeline FPGA top](https://github.com/ritu235/3-stage-pipeline/blob/main/full_pipeline/top_fpga.v): `full_pipeline/top_fpga.v`

### Program images

- [Binary images](https://github.com/ritu235/3-stage-pipeline/blob/main/Pipeline_via_terminal/mem_generator/imem_dmem/imem.bin): `Pipeline_via_terminal/mem_generator/imem_dmem/imem.bin`
- [Image converter](https://github.com/ritu235/3-stage-pipeline/blob/main/Pipeline_via_terminal/mem_generator/imem_dmem/bin2hex.py): `Pipeline_via_terminal/mem_generator/imem_dmem/bin2hex.py`
- [Hex images](https://github.com/ritu235/3-stage-pipeline/blob/main/Pipeline_via_terminal/mem_generator/imem_dmem/imem.hex): `Pipeline_via_terminal/mem_generator/imem_dmem/imem.hex`
- [Integrated hex images](https://github.com/ritu235/3-stage-pipeline/blob/main/full_pipeline/imem.hex): `full_pipeline/imem.hex`
- [Memory-lab hex image](https://github.com/ritu235/3-stage-pipeline/blob/main/memory/imem.hex): `memory/imem.hex`

## Connections

- Binary images → Image converter: reads
- Image converter → Hex images: writes