How ritesh-belgudri/project_deccan works
Project Deccan is an FPGA design framework: users select a Verilog example and board, then use the designs Makefile to build a bitstream, run simulations, inspect reports, or program a device. The README documents the tool stages and optional programming and waveform flows. The Makefile and most flow implementation were not sampled, so orchestration links follow documented behavior; no finer internal call structure is inferred.
Main entry points: Makefile Build workflow · led_blink_sim.cpp Blink simulation driver · ping_pong_led_sim.cpp Ping-pong simulation driver · designs Waveform output
Components 22
Build and analysis
- Build workflow
designs/Makefile - Yosys synthesis
- Place and route
- Timing analysis
- Bitstream packer
- Design reports
designs/Makefile - Build outputs
designs
FPGA designs
- LED blinker
designs/led_blink/led_blink.v - Blink top module
designs/led_blink/top.v - Ping-pong LEDs
designs/ping_pong_led/ping_pong_led.v - Ping-pong top module
designs/ping_pong_led/top.v
Simulation
- Verilator simulator
- Blink simulation driver
designs/led_blink/led_blink_sim.cpp - Ping-pong simulation driver
designs/ping_pong_led/ping_pong_led_sim.cpp - Waveform output
designs - Waveform viewer
Device support
- Board constraints
designs/boards - UPduino constraints
designs/boards/lattice/upduino2_v2/upduino_v2.pcf - MDP constraints
designs/boards/lattice/ice40-mdp/io_mdp_u3.pcf - Device programming
tools/icestorm - FPGA board
Other components
- Engineer
Connections 27
- Engineer → Build workflow: selects target
- Build workflow → Yosys synthesis: synthesizes Verilog
- Yosys synthesis → Place and route: passes JSON
- Build workflow → Place and route: routes design
- Build workflow → Timing analysis: analyzes timing
- Build workflow → Bitstream packer: packs bitstream
- Build workflow → Design reports: generates reports
- Yosys synthesis → Design reports: reports utilization
- Timing analysis → Design reports: reports timing
- Build workflow → Build outputs: writes outputs
- LED blinker → Build workflow: selected source
- Blink top module → Build workflow: selected source
- Ping-pong LEDs → Build workflow: selected source
- Ping-pong top module → Build workflow: selected source
- UPduino constraints → Build workflow: board selection
- MDP constraints → Build workflow: board selection
- Build workflow → Device programming: programs device
- Device programming → FPGA board: loads bitstream
- Engineer → Build workflow: requests simulation
- Build workflow → Verilator simulator: runs simulation
- Build workflow → Blink simulation driver: builds driver
- Build workflow → Ping-pong simulation driver: builds driver
- Blink simulation driver → Verilator simulator: drives model
- Ping-pong simulation driver → Verilator simulator: drives model
- Verilator simulator → Waveform output: writes VCD
- Engineer → Waveform viewer: views waveform
- Waveform output → Waveform viewer: opens trace