# ritesh-belgudri/project_deccan architecture

> Architecture diagram of the GitHub repository ritesh-belgudri/project_deccan, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-27). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/ritesh-belgudri/project_deccan
- Repository: https://github.com/ritesh-belgudri/project_deccan

## Overview

Project Deccan is an FPGA design framework: users select a Verilog example and board, then use the designs Makefile to build a bitstream, run simulations, inspect reports, or program a device. The README documents the tool stages and optional programming and waveform flows. The Makefile and most flow implementation were not sampled, so orchestration links follow documented behavior; no finer internal call structure is inferred.

Main entry points: [`designs/Makefile`](https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/Makefile) (Build workflow), [`designs/led_blink/led_blink_sim.cpp`](https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/led_blink/led_blink_sim.cpp) (Blink simulation driver), [`designs/ping_pong_led/ping_pong_led_sim.cpp`](https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/ping_pong_led/ping_pong_led_sim.cpp) (Ping-pong simulation driver), [`designs`](https://github.com/ritesh-belgudri/project_deccan/tree/main/designs) (Waveform output)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_flow["Build and analysis"]
  node_makeflow["Build workflow"]
  node_yosys["Yosys synthesis"]
  node_nextpnr["Place and route"]
  node_icetime["Timing analysis"]
  node_icepack["Bitstream packer"]
  node_reports["Design reports"]
  node_artifacts["Build outputs"]
end

subgraph group_designs["FPGA designs"]
  node_blink["LED blinker<br/>[led_blink.v]"]
  node_blinktop["Blink top module<br/>[top.v]"]
  node_pingpong["Ping-pong LEDs<br/>[ping_pong_led.v]"]
  node_pingtop["Ping-pong top module<br/>[top.v]"]
end

subgraph group_simulation["Simulation"]
  node_verilator["Verilator simulator"]
  node_blinkwrapper["Blink simulation driver<br/>[led_blink_sim.cpp]"]
  node_pingwrapper["Ping-pong simulation driver"]
  node_waveform["Waveform output"]
  node_viewer["Waveform viewer"]
end

subgraph group_hardware["Device support"]
  node_boards["Board constraints"]
  node_upduino["UPduino constraints<br/>[upduino_v2.pcf]"]
  node_mdp["MDP constraints<br/>[io_mdp_u3.pcf]"]
  node_programmer["Device programming"]
  node_fpga["FPGA board"]
end

node_engineer(("Engineer"))

node_engineer -->|"selects target"| node_makeflow
node_makeflow -->|"synthesizes Verilog"| node_yosys
node_yosys -->|"passes JSON"| node_nextpnr
node_makeflow -->|"routes design"| node_nextpnr
node_makeflow -->|"analyzes timing"| node_icetime
node_makeflow -->|"packs bitstream"| node_icepack
node_makeflow -->|"generates reports"| node_reports
node_yosys -->|"reports utilization"| node_reports
node_icetime -->|"reports timing"| node_reports
node_makeflow -->|"writes outputs"| node_artifacts
node_blink -->|"selected source"| node_makeflow
node_blinktop -->|"selected source"| node_makeflow
node_pingpong -->|"selected source"| node_makeflow
node_pingtop -->|"selected source"| node_makeflow
node_upduino -->|"board selection"| node_makeflow
node_mdp -->|"board selection"| node_makeflow
node_makeflow -.->|"programs device"| node_programmer
node_programmer -.->|"loads bitstream"| node_fpga
node_engineer -->|"requests simulation"| node_makeflow
node_makeflow -->|"runs simulation"| node_verilator
node_makeflow -->|"builds driver"| node_blinkwrapper
node_makeflow -->|"builds driver"| node_pingwrapper
node_blinkwrapper -->|"drives model"| node_verilator
node_pingwrapper -->|"drives model"| node_verilator
node_verilator -->|"writes VCD"| node_waveform
node_engineer -.->|"views waveform"| node_viewer
node_waveform -.->|"opens trace"| node_viewer

click node_makeflow "https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/Makefile"
click node_reports "https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/Makefile"
click node_artifacts "https://github.com/ritesh-belgudri/project_deccan/tree/main/designs"
click node_blink "https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/led_blink/led_blink.v"
click node_blinktop "https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/led_blink/top.v"
click node_pingpong "https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/ping_pong_led/ping_pong_led.v"
click node_pingtop "https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/ping_pong_led/top.v"
click node_boards "https://github.com/ritesh-belgudri/project_deccan/tree/main/designs/boards"
click node_upduino "https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/boards/lattice/upduino2_v2/upduino_v2.pcf"
click node_mdp "https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/boards/lattice/ice40-mdp/io_mdp_u3.pcf"
click node_programmer "https://github.com/ritesh-belgudri/project_deccan/tree/main/tools/icestorm"
click node_blinkwrapper "https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/led_blink/led_blink_sim.cpp"
click node_pingwrapper "https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/ping_pong_led/ping_pong_led_sim.cpp"
click node_waveform "https://github.com/ritesh-belgudri/project_deccan/tree/main/designs"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_makeflow,node_yosys,node_nextpnr,node_icetime,node_icepack,node_reports,node_artifacts toneBlue
class node_blink,node_blinktop,node_pingpong,node_pingtop toneAmber
class node_verilator,node_blinkwrapper,node_pingwrapper,node_waveform,node_viewer toneMint
class node_boards,node_upduino,node_mdp,node_programmer,node_fpga toneRose
class node_engineer toneIndigo
```

## Components

### Build and analysis

- [Build workflow](https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/Makefile): `designs/Makefile`
- **Yosys synthesis**
- **Place and route**
- **Timing analysis**
- **Bitstream packer**
- [Design reports](https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/Makefile): `designs/Makefile`
- [Build outputs](https://github.com/ritesh-belgudri/project_deccan/tree/main/designs): `designs`

### FPGA designs

- [LED blinker](https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/led_blink/led_blink.v): `designs/led_blink/led_blink.v`
- [Blink top module](https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/led_blink/top.v): `designs/led_blink/top.v`
- [Ping-pong LEDs](https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/ping_pong_led/ping_pong_led.v): `designs/ping_pong_led/ping_pong_led.v`
- [Ping-pong top module](https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/ping_pong_led/top.v): `designs/ping_pong_led/top.v`

### Simulation

- **Verilator simulator**
- [Blink simulation driver](https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/led_blink/led_blink_sim.cpp): `designs/led_blink/led_blink_sim.cpp`
- [Ping-pong simulation driver](https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/ping_pong_led/ping_pong_led_sim.cpp): `designs/ping_pong_led/ping_pong_led_sim.cpp`
- [Waveform output](https://github.com/ritesh-belgudri/project_deccan/tree/main/designs): `designs`
- **Waveform viewer**

### Device support

- [Board constraints](https://github.com/ritesh-belgudri/project_deccan/tree/main/designs/boards): `designs/boards`
- [UPduino constraints](https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/boards/lattice/upduino2_v2/upduino_v2.pcf): `designs/boards/lattice/upduino2_v2/upduino_v2.pcf`
- [MDP constraints](https://github.com/ritesh-belgudri/project_deccan/blob/main/designs/boards/lattice/ice40-mdp/io_mdp_u3.pcf): `designs/boards/lattice/ice40-mdp/io_mdp_u3.pcf`
- [Device programming](https://github.com/ritesh-belgudri/project_deccan/tree/main/tools/icestorm): `tools/icestorm`
- **FPGA board**

### Other components

- **Engineer**

## Connections

- Engineer → Build workflow: selects target
- Build workflow → Yosys synthesis: synthesizes Verilog
- Yosys synthesis → Place and route: passes JSON
- Build workflow → Place and route: routes design
- Build workflow → Timing analysis: analyzes timing
- Build workflow → Bitstream packer: packs bitstream
- Build workflow → Design reports: generates reports
- Yosys synthesis → Design reports: reports utilization
- Timing analysis → Design reports: reports timing
- Build workflow → Build outputs: writes outputs
- LED blinker → Build workflow: selected source
- Blink top module → Build workflow: selected source
- Ping-pong LEDs → Build workflow: selected source
- Ping-pong top module → Build workflow: selected source
- UPduino constraints → Build workflow: board selection
- MDP constraints → Build workflow: board selection
- Build workflow → Device programming: programs device
- Device programming → FPGA board: loads bitstream
- Engineer → Build workflow: requests simulation
- Build workflow → Verilator simulator: runs simulation
- Build workflow → Blink simulation driver: builds driver
- Build workflow → Ping-pong simulation driver: builds driver
- Blink simulation driver → Verilator simulator: drives model
- Ping-pong simulation driver → Verilator simulator: drives model
- Verilator simulator → Waveform output: writes VCD
- Engineer → Waveform viewer: views waveform
- Waveform output → Waveform viewer: opens trace