How raydmr/fieldorientedcontrol works
This repository is an experimental MATLAB/Simulink field-oriented control (FOC) project with generated VHDL intended as an FPGA-synthesis input. The documented workflow is to run the parameter script, open and simulate the Simulink model, and use HDL-generated VHDL downstream. The VHDL filenames identify controller and coordinate-transform modules, but no source excerpts show their wiring, so those relationships are not asserted. The README cautions that generated code is not validated beyond MathWorks tools.
Main entry points: FOC.slx FOC model · foc_controlsystem_param.m Model parameters · FOC.vhd FOC HDL top
Components 15
Modeling and simulation
- Model parameters
foc_controlsystem_param.m - FOC model
FOC.slx
FOC control
- Velocity controller
FOC VHDL/VelocityController.vhd - Current controller
FOC VHDL/CurrentController.vhd - Id controller
FOC VHDL/IdController.vhd - Iq controller
FOC VHDL/IqController.vhd - PID controller
FOC VHDL/PIDController.vhd - Decoupling
FOC VHDL/Decoupling.vhd
Coordinate transforms
- Park transform
FOC VHDL/Park_Transform.vhd - Inverse Park transform
FOC VHDL/Inverse_Park_Transform.vhd - ABC to dq
FOC VHDL/abc2dq.vhd - dq to ABC
FOC VHDL/dq2abc.vhd
Generated HDL
- FOC HDL top
FOC VHDL/FOC.vhd
Other components
- Engineer
- FPGA synthesis environment
Connections 5
- Engineer → Model parameters: runs
README.md - Engineer → FOC model: opens and runs
README.md - Model parameters → FOC model: sets parameters
README.md - FOC model → FOC HDL top: generates HDL
README.md - FOC HDL top → FPGA synthesis environment: intended for synthesis
README.md