# raydmr/fieldorientedcontrol architecture

> Architecture diagram of the GitHub repository raydmr/fieldorientedcontrol, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-11-15). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/raydmr/fieldorientedcontrol
- Repository: https://github.com/raydmr/fieldorientedcontrol

## Overview

This repository is an experimental MATLAB/Simulink field-oriented control (FOC) project with generated VHDL intended as an FPGA-synthesis input. The documented workflow is to run the parameter script, open and simulate the Simulink model, and use HDL-generated VHDL downstream. The VHDL filenames identify controller and coordinate-transform modules, but no source excerpts show their wiring, so those relationships are not asserted. The README cautions that generated code is not validated beyond MathWorks tools.

Main entry points: [`FOC.slx`](https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC.slx) (FOC model), [`foc_controlsystem_param.m`](https://github.com/raydmr/fieldorientedcontrol/blob/master/foc_controlsystem_param.m) (Model parameters), [`FOC VHDL/FOC.vhd`](https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/FOC.vhd) (FOC HDL top)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_modeling["Modeling and simulation"]
  node_params["Model parameters"]
  node_simulink_model["FOC model<br/>[FOC.slx]"]
end

subgraph group_control["FOC control"]
  node_velocity["Velocity controller"]
  node_current["Current controller"]
  node_id["Id controller<br/>[IdController.vhd]"]
  node_iq["Iq controller<br/>[IqController.vhd]"]
  node_pid["PID controller<br/>[PIDController.vhd]"]
  node_decoupling["Decoupling<br/>[Decoupling.vhd]"]
end

subgraph group_transforms["Coordinate transforms"]
  node_park["Park transform<br/>[Park_Transform.vhd]"]
  node_inverse_park["Inverse Park transform"]
  node_abc_dq["ABC to dq<br/>[abc2dq.vhd]"]
  node_dq_abc["dq to ABC<br/>[dq2abc.vhd]"]
end

subgraph group_hdl["Generated HDL"]
  node_foc_top["FOC HDL top<br/>[FOC.vhd]"]
end

node_engineer(("Engineer"))
node_fpga["FPGA synthesis environment"]

node_engineer -->|"runs"| node_params
node_engineer -->|"opens and runs"| node_simulink_model
node_params -->|"sets parameters"| node_simulink_model
node_simulink_model -->|"generates HDL"| node_foc_top
node_foc_top -->|"intended for synthesis"| node_fpga

click node_params "https://github.com/raydmr/fieldorientedcontrol/blob/master/foc_controlsystem_param.m"
click node_simulink_model "https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC.slx"
click node_foc_top "https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/FOC.vhd"
click node_velocity "https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/VelocityController.vhd"
click node_current "https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/CurrentController.vhd"
click node_id "https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/IdController.vhd"
click node_iq "https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/IqController.vhd"
click node_pid "https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/PIDController.vhd"
click node_decoupling "https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/Decoupling.vhd"
click node_park "https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/Park_Transform.vhd"
click node_inverse_park "https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/Inverse_Park_Transform.vhd"
click node_abc_dq "https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/abc2dq.vhd"
click node_dq_abc "https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/dq2abc.vhd"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_params,node_simulink_model toneBlue
class node_velocity,node_current,node_id,node_iq,node_pid,node_decoupling toneAmber
class node_park,node_inverse_park,node_abc_dq,node_dq_abc toneMint
class node_foc_top toneRose
class node_engineer,node_fpga toneIndigo
```

## Components

### Modeling and simulation

- [Model parameters](https://github.com/raydmr/fieldorientedcontrol/blob/master/foc_controlsystem_param.m): `foc_controlsystem_param.m`
- [FOC model](https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC.slx): `FOC.slx`

### FOC control

- [Velocity controller](https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/VelocityController.vhd): `FOC VHDL/VelocityController.vhd`
- [Current controller](https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/CurrentController.vhd): `FOC VHDL/CurrentController.vhd`
- [Id controller](https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/IdController.vhd): `FOC VHDL/IdController.vhd`
- [Iq controller](https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/IqController.vhd): `FOC VHDL/IqController.vhd`
- [PID controller](https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/PIDController.vhd): `FOC VHDL/PIDController.vhd`
- [Decoupling](https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/Decoupling.vhd): `FOC VHDL/Decoupling.vhd`

### Coordinate transforms

- [Park transform](https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/Park_Transform.vhd): `FOC VHDL/Park_Transform.vhd`
- [Inverse Park transform](https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/Inverse_Park_Transform.vhd): `FOC VHDL/Inverse_Park_Transform.vhd`
- [ABC to dq](https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/abc2dq.vhd): `FOC VHDL/abc2dq.vhd`
- [dq to ABC](https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/dq2abc.vhd): `FOC VHDL/dq2abc.vhd`

### Generated HDL

- [FOC HDL top](https://github.com/raydmr/fieldorientedcontrol/blob/master/FOC%20VHDL/FOC.vhd): `FOC VHDL/FOC.vhd`

### Other components

- **Engineer**
- **FPGA synthesis environment**

## Connections

- Engineer → Model parameters: runs (evidence: `README.md`)
- Engineer → FOC model: opens and runs (evidence: `README.md`)
- Model parameters → FOC model: sets parameters (evidence: `README.md`)
- FOC model → FOC HDL top: generates HDL (evidence: `README.md`)
- FOC HDL top → FPGA synthesis environment: intended for synthesis (evidence: `README.md`)