How raghavrv/verilog works
This repository is a collection of Verilog digital-logic designs, not a single application with a documented runtime workflow. Its modules cover combinational arithmetic and code conversion, sequential storage and counters, data selection and encoding, and basic gates. The file tree supports these capability groupings, but no README or source excerpts establish how modules call or connect to one another. Accordingly, the graph shows the designs as independent components and omits speculative wiring and user-flow edges.
Components 34
Arithmetic and comparison
- 4-bit multiplier
4BitMultiplier.v - 4-bit parallel adder
4BitParalleladder.v - 4-bit ripple adder
4bit ripplecarry adder.v - 8-bit ripple adder
8bitRippleCarryAdder.v - Structural full adder
full_adder_strucmodel.v - Half adder
half_adder.v - Dataflow full subtractor
full_sub_dataflow.v - Full subtractor
full_sub.v - Half subtractor
half_sub.v - Two-bit comparator
TwoBitMagComp.v - One-bit comparator
oneBitMagComparator.v
Code conversion
- BCD to Excess-3
bcd_excess3.v - Excess-3 to BCD
excess3tobcd.v - Binary to Gray
bin_gray.v - Gray to binary
graytoBin.v - BCD seven-segment
bcd_7seg.v
Sequential logic
- D flip-flop
DFlipFlop.v - D from JK
DUsingJK.v - JK flip-flop
jkFlipFlop.v - T flip-flop
TFlipFlop.v - T from JK
TUsingJK.v - 4-bit up/down counter
4bit UpdownCounter.v - 4-bit synchronous counter
4bit synch counter.v - 4-bit asynchronous counter
4bitAsynchcounter.v - Mod-10 counter
countermod10.v - Accumulator model
Accumulator Model.v - Pseudo-random bit generator
Psudo random bit generator.v - Parallel-in parallel-out
pipo.v - Parallel-in serial-out
piso.v - Serial-in parallel-out
sipo.v - Serial-in serial-out
siso.v
Selection and encoding
- 8-to-3 encoder
Encoder8by3.v - Priority encoder
pEncoder.v - 2-to-4 decoder
decoder2by4.v