# raghavrv/verilog architecture

> Architecture diagram of the GitHub repository raghavrv/verilog, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-27). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/raghavrv/verilog
- Repository: https://github.com/raghavrv/verilog

## Overview

This repository is a collection of Verilog digital-logic designs, not a single application with a documented runtime workflow. Its modules cover combinational arithmetic and code conversion, sequential storage and counters, data selection and encoding, and basic gates. The file tree supports these capability groupings, but no README or source excerpts establish how modules call or connect to one another. Accordingly, the graph shows the designs as independent components and omits speculative wiring and user-flow edges.

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_arithmetic["Arithmetic and comparison"]
  node_multiplier4["4-bit multiplier<br/>[4BitMultiplier.v]"]
  node_parallel_adder4["4-bit parallel adder"]
  node_ripple_adder4["4-bit ripple adder"]
  node_ripple_adder8["8-bit ripple adder"]
  node_full_adder_structural["Structural full adder"]
  node_half_adder["Half adder<br/>[half_adder.v]"]
  node_full_sub_dataflow["Dataflow full subtractor"]
  node_full_sub["Full subtractor<br/>[full_sub.v]"]
  node_half_sub["Half subtractor<br/>[half_sub.v]"]
  node_comparator2["Two-bit comparator<br/>[TwoBitMagComp.v]"]
  node_comparator1["One-bit comparator"]
end

subgraph group_conversion["Code conversion"]
  node_bcd_excess3["BCD to Excess-3<br/>[bcd_excess3.v]"]
  node_excess3_bcd["Excess-3 to BCD<br/>[excess3tobcd.v]"]
  node_binary_gray["Binary to Gray<br/>[bin_gray.v]"]
  node_gray_binary["Gray to binary<br/>[graytoBin.v]"]
  node_bcd_display["BCD seven-segment<br/>[bcd_7seg.v]"]
end

subgraph group_sequential["Sequential logic"]
  node_d_flipflop["D flip-flop<br/>[DFlipFlop.v]"]
  node_d_using_jk["D from JK<br/>[DUsingJK.v]"]
  node_jk_flipflop["JK flip-flop<br/>[jkFlipFlop.v]"]
  node_t_flipflop["T flip-flop<br/>[TFlipFlop.v]"]
  node_t_using_jk["T from JK<br/>[TUsingJK.v]"]
  node_counter_updown["4-bit up/down counter"]
  node_counter_sync["4-bit synchronous counter"]
  node_counter_async["4-bit asynchronous counter"]
  node_counter_mod10["Mod-10 counter<br/>[countermod10.v]"]
  node_accumulator["Accumulator model"]
  node_prng["Pseudo-random bit generator"]
  node_pipo["Parallel-in parallel-out<br/>[pipo.v]"]
  node_piso["Parallel-in serial-out<br/>[piso.v]"]
  node_sipo["Serial-in parallel-out<br/>[sipo.v]"]
  node_siso["Serial-in serial-out<br/>[siso.v]"]
end

subgraph group_routing["Selection and encoding"]
  node_encoder8["8-to-3 encoder<br/>[Encoder8by3.v]"]
  node_priority_encoder["Priority encoder<br/>[pEncoder.v]"]
  node_decoder2["2-to-4 decoder<br/>[decoder2by4.v]"]
end

subgraph group_primitives["Logic primitives"]
end

click node_multiplier4 "https://github.com/raghavrv/verilog/blob/master/4BitMultiplier.v"
click node_parallel_adder4 "https://github.com/raghavrv/verilog/blob/master/4BitParalleladder.v"
click node_ripple_adder4 "https://github.com/raghavrv/verilog/blob/master/4bit%20ripplecarry%20adder.v"
click node_ripple_adder8 "https://github.com/raghavrv/verilog/blob/master/8bitRippleCarryAdder.v"
click node_full_adder_structural "https://github.com/raghavrv/verilog/blob/master/full_adder_strucmodel.v"
click node_half_adder "https://github.com/raghavrv/verilog/blob/master/half_adder.v"
click node_full_sub_dataflow "https://github.com/raghavrv/verilog/blob/master/full_sub_dataflow.v"
click node_full_sub "https://github.com/raghavrv/verilog/blob/master/full_sub.v"
click node_half_sub "https://github.com/raghavrv/verilog/blob/master/half_sub.v"
click node_comparator2 "https://github.com/raghavrv/verilog/blob/master/TwoBitMagComp.v"
click node_comparator1 "https://github.com/raghavrv/verilog/blob/master/oneBitMagComparator.v"
click node_bcd_excess3 "https://github.com/raghavrv/verilog/blob/master/bcd_excess3.v"
click node_excess3_bcd "https://github.com/raghavrv/verilog/blob/master/excess3tobcd.v"
click node_binary_gray "https://github.com/raghavrv/verilog/blob/master/bin_gray.v"
click node_gray_binary "https://github.com/raghavrv/verilog/blob/master/graytoBin.v"
click node_bcd_display "https://github.com/raghavrv/verilog/blob/master/bcd_7seg.v"
click node_d_flipflop "https://github.com/raghavrv/verilog/blob/master/DFlipFlop.v"
click node_d_using_jk "https://github.com/raghavrv/verilog/blob/master/DUsingJK.v"
click node_jk_flipflop "https://github.com/raghavrv/verilog/blob/master/jkFlipFlop.v"
click node_t_flipflop "https://github.com/raghavrv/verilog/blob/master/TFlipFlop.v"
click node_t_using_jk "https://github.com/raghavrv/verilog/blob/master/TUsingJK.v"
click node_counter_updown "https://github.com/raghavrv/verilog/blob/master/4bit%20UpdownCounter.v"
click node_counter_sync "https://github.com/raghavrv/verilog/blob/master/4bit%20synch%20counter.v"
click node_counter_async "https://github.com/raghavrv/verilog/blob/master/4bitAsynchcounter.v"
click node_counter_mod10 "https://github.com/raghavrv/verilog/blob/master/countermod10.v"
click node_accumulator "https://github.com/raghavrv/verilog/blob/master/Accumulator%20Model.v"
click node_prng "https://github.com/raghavrv/verilog/blob/master/Psudo%20random%20bit%20generator.v"
click node_pipo "https://github.com/raghavrv/verilog/blob/master/pipo.v"
click node_piso "https://github.com/raghavrv/verilog/blob/master/piso.v"
click node_sipo "https://github.com/raghavrv/verilog/blob/master/sipo.v"
click node_siso "https://github.com/raghavrv/verilog/blob/master/siso.v"
click node_encoder8 "https://github.com/raghavrv/verilog/blob/master/Encoder8by3.v"
click node_priority_encoder "https://github.com/raghavrv/verilog/blob/master/pEncoder.v"
click node_decoder2 "https://github.com/raghavrv/verilog/blob/master/decoder2by4.v"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_multiplier4,node_parallel_adder4,node_ripple_adder4,node_ripple_adder8,node_full_adder_structural,node_half_adder,node_full_sub_dataflow,node_full_sub,node_half_sub,node_comparator2,node_comparator1 toneBlue
class node_bcd_excess3,node_excess3_bcd,node_binary_gray,node_gray_binary,node_bcd_display toneAmber
class node_d_flipflop,node_d_using_jk,node_jk_flipflop,node_t_flipflop,node_t_using_jk,node_counter_updown,node_counter_sync,node_counter_async,node_counter_mod10,node_accumulator,node_prng,node_pipo,node_piso,node_sipo,node_siso toneMint
class node_encoder8,node_priority_encoder,node_decoder2 toneRose
```

## Components

### Arithmetic and comparison

- [4-bit multiplier](https://github.com/raghavrv/verilog/blob/master/4BitMultiplier.v): `4BitMultiplier.v`
- [4-bit parallel adder](https://github.com/raghavrv/verilog/blob/master/4BitParalleladder.v): `4BitParalleladder.v`
- [4-bit ripple adder](https://github.com/raghavrv/verilog/blob/master/4bit%20ripplecarry%20adder.v): `4bit ripplecarry adder.v`
- [8-bit ripple adder](https://github.com/raghavrv/verilog/blob/master/8bitRippleCarryAdder.v): `8bitRippleCarryAdder.v`
- [Structural full adder](https://github.com/raghavrv/verilog/blob/master/full_adder_strucmodel.v): `full_adder_strucmodel.v`
- [Half adder](https://github.com/raghavrv/verilog/blob/master/half_adder.v): `half_adder.v`
- [Dataflow full subtractor](https://github.com/raghavrv/verilog/blob/master/full_sub_dataflow.v): `full_sub_dataflow.v`
- [Full subtractor](https://github.com/raghavrv/verilog/blob/master/full_sub.v): `full_sub.v`
- [Half subtractor](https://github.com/raghavrv/verilog/blob/master/half_sub.v): `half_sub.v`
- [Two-bit comparator](https://github.com/raghavrv/verilog/blob/master/TwoBitMagComp.v): `TwoBitMagComp.v`
- [One-bit comparator](https://github.com/raghavrv/verilog/blob/master/oneBitMagComparator.v): `oneBitMagComparator.v`

### Code conversion

- [BCD to Excess-3](https://github.com/raghavrv/verilog/blob/master/bcd_excess3.v): `bcd_excess3.v`
- [Excess-3 to BCD](https://github.com/raghavrv/verilog/blob/master/excess3tobcd.v): `excess3tobcd.v`
- [Binary to Gray](https://github.com/raghavrv/verilog/blob/master/bin_gray.v): `bin_gray.v`
- [Gray to binary](https://github.com/raghavrv/verilog/blob/master/graytoBin.v): `graytoBin.v`
- [BCD seven-segment](https://github.com/raghavrv/verilog/blob/master/bcd_7seg.v): `bcd_7seg.v`

### Sequential logic

- [D flip-flop](https://github.com/raghavrv/verilog/blob/master/DFlipFlop.v): `DFlipFlop.v`
- [D from JK](https://github.com/raghavrv/verilog/blob/master/DUsingJK.v): `DUsingJK.v`
- [JK flip-flop](https://github.com/raghavrv/verilog/blob/master/jkFlipFlop.v): `jkFlipFlop.v`
- [T flip-flop](https://github.com/raghavrv/verilog/blob/master/TFlipFlop.v): `TFlipFlop.v`
- [T from JK](https://github.com/raghavrv/verilog/blob/master/TUsingJK.v): `TUsingJK.v`
- [4-bit up/down counter](https://github.com/raghavrv/verilog/blob/master/4bit%20UpdownCounter.v): `4bit UpdownCounter.v`
- [4-bit synchronous counter](https://github.com/raghavrv/verilog/blob/master/4bit%20synch%20counter.v): `4bit synch counter.v`
- [4-bit asynchronous counter](https://github.com/raghavrv/verilog/blob/master/4bitAsynchcounter.v): `4bitAsynchcounter.v`
- [Mod-10 counter](https://github.com/raghavrv/verilog/blob/master/countermod10.v): `countermod10.v`
- [Accumulator model](https://github.com/raghavrv/verilog/blob/master/Accumulator%20Model.v): `Accumulator Model.v`
- [Pseudo-random bit generator](https://github.com/raghavrv/verilog/blob/master/Psudo%20random%20bit%20generator.v): `Psudo random bit generator.v`
- [Parallel-in parallel-out](https://github.com/raghavrv/verilog/blob/master/pipo.v): `pipo.v`
- [Parallel-in serial-out](https://github.com/raghavrv/verilog/blob/master/piso.v): `piso.v`
- [Serial-in parallel-out](https://github.com/raghavrv/verilog/blob/master/sipo.v): `sipo.v`
- [Serial-in serial-out](https://github.com/raghavrv/verilog/blob/master/siso.v): `siso.v`

### Selection and encoding

- [8-to-3 encoder](https://github.com/raghavrv/verilog/blob/master/Encoder8by3.v): `Encoder8by3.v`
- [Priority encoder](https://github.com/raghavrv/verilog/blob/master/pEncoder.v): `pEncoder.v`
- [2-to-4 decoder](https://github.com/raghavrv/verilog/blob/master/decoder2by4.v): `decoder2by4.v`